Lines Matching defs:shader
674 * albeit the amd gpu shader analyser
2243 if (rctx->vs_shader->current->shader.vs_as_ls) {
2323 struct r600_pipe_shader *stage = rctx->hw_shader_stages[i].shader;
2367 if (rctx->vs_shader->current->shader.vs_as_ls) {
2482 if (rctx->vs_shader->current->shader.vs_as_ls) {
2548 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2550 if (!shader)
2554 (shader->buffer->gpu_address + shader->offset) >> 8);
2556 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
2568 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
2593 if (rctx->gs_shader->current->shader.gs_prim_id_input)
3313 void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3316 struct r600_command_buffer *cb = &shader->command_buffer;
3317 struct r600_shader *rshader = &shader->shader;
3425 if (shader->selector->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
3427 S_02880C_EXEC_ON_NOOP(shader->selector->info.writes_memory);
3428 } else if (shader->selector->info.writes_memory) {
3460 shader->nr_ps_color_outputs = num_cout;
3461 shader->ps_color_export_mask = rshader->ps_color_export_mask;
3502 r600_store_value(cb, shader->bo->gpu_address >> 8);
3508 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3510 shader->db_shader_control = db_shader_control;
3511 shader->ps_depth_export = z_export | stencil_export | mask_export;
3513 shader->sprite_coord_enable = sprite_coord_enable;
3514 shader->flatshade = flatshade;
3515 shader->msaa = msaa;
3518 void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3520 struct r600_command_buffer *cb = &shader->command_buffer;
3521 struct r600_shader *rshader = &shader->shader;
3530 shader->bo->gpu_address >> 8);
3531 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3534 void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3536 struct r600_command_buffer *cb = &shader->command_buffer;
3537 struct r600_shader *rshader = &shader->shader;
3538 struct r600_shader *cp_shader = &shader->gs_copy_shader->shader;
3540 (cp_shader->ring_item_sizes[0] * shader->selector->gs_max_out_vertices) >> 2,
3541 (cp_shader->ring_item_sizes[1] * shader->selector->gs_max_out_vertices) >> 2,
3542 (cp_shader->ring_item_sizes[2] * shader->selector->gs_max_out_vertices) >> 2,
3543 (cp_shader->ring_item_sizes[3] * shader->selector->gs_max_out_vertices) >> 2
3552 S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices));
3554 r600_conv_prim_to_gs_out(shader->selector->gs_output_prim));
3557 S_028B90_CNT(MIN2(shader->selector->gs_num_invocations, 127)) |
3558 S_028B90_ENABLE(shader->selector->gs_num_invocations > 0));
3590 shader->bo->gpu_address >> 8);
3591 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3595 void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3597 struct r600_command_buffer *cb = &shader->command_buffer;
3598 struct r600_shader *rshader = &shader->shader;
3642 shader->bo->gpu_address >> 8);
3643 /* After that, the NOP relocation packet must be emitted (shader->bo, RADEON_USAGE_READ). */
3645 shader->pa_cl_vs_out_cntl =
3655 void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3657 struct r600_command_buffer *cb = &shader->command_buffer;
3658 struct r600_shader *rshader = &shader->shader;
3666 shader->bo->gpu_address >> 8);
3669 void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3671 struct r600_command_buffer *cb = &shader->command_buffer;
3672 struct r600_shader *rshader = &shader->shader;
3680 shader->bo->gpu_address >> 8);
3742 * shader execution.
3745 * write to the zbuffer. Write to zbuffer is delayed after fragment shader
4059 enum pipe_shader_type shader, unsigned start_slot,
4073 if (shader != PIPE_SHADER_FRAGMENT &&
4074 shader != PIPE_SHADER_COMPUTE && count == 0)
4077 if (shader == PIPE_SHADER_FRAGMENT)
4079 else if (shader == PIPE_SHADER_COMPUTE)
4154 if (shader == PIPE_SHADER_FRAGMENT)
4159 enum pipe_shader_type shader, unsigned start_slot,
4174 if (shader != PIPE_SHADER_FRAGMENT && shader != PIPE_SHADER_COMPUTE)
4179 if (shader == PIPE_SHADER_FRAGMENT)
4181 else if (shader == PIPE_SHADER_COMPUTE)
4184 assert (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE);
4343 if (shader == PIPE_SHADER_FRAGMENT)
4348 enum pipe_shader_type shader, uint slot,
4351 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
4362 enum pipe_shader_type shader,
4366 assert(shader == PIPE_SHADER_COMPUTE);
4396 st->saved_compute = rctx->cs_shader_state.shader;
4427 /* shader const */
4434 /* shader program */
4673 if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader) {
4685 /* gather required shader gprs */
4687 if (rctx->hw_shader_stages[i].shader)
4688 num_gprs[i] = rctx->hw_shader_stages[i].shader->shader.bc.ngpr;
4913 pshader = rctx->hw_shader_stages[i].shader;
4917 num_atomic_stage = pshader->shader.nhwatomic_ranges;
4922 struct r600_shader_atomic *atomic = &pshader->shader.atomics[j];