Lines Matching refs:rctx
127 struct r600_context *rctx = NULL;
133 rctx = pipe->ctx;
135 COMPUTE_DBG(rctx->screen, "bind rat: %i \n", id);
161 evergreen_init_color_surface_rat(rctx, surf);
164 static void evergreen_cs_set_vertex_buffer(struct r600_context *rctx,
169 struct r600_vertexbuf_state *state = &rctx->cs_vertex_buffer_state;
178 rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE;
181 r600_mark_atom_dirty(rctx, &state->atom);
184 static void evergreen_cs_set_constant_buffer(struct r600_context *rctx,
196 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_COMPUTE, cb_index, false, &cb);
429 struct r600_context *rctx = (struct r600_context *)ctx;
437 shader->ctx = rctx;
457 COMPUTE_DBG(rctx->screen, "*** evergreen_create_compute_state\n");
464 shader->code_bo = r600_compute_buffer_alloc_vram(rctx->screen,
467 &rctx->b, shader->code_bo,
471 rctx->b.ws->buffer_unmap(rctx->b.ws, shader->code_bo->buf);
479 struct r600_context *rctx = (struct r600_context *)ctx;
482 COMPUTE_DBG(rctx->screen, "*** evergreen_delete_compute_state\n");
503 struct r600_context *rctx = (struct r600_context *)ctx;
505 COMPUTE_DBG(rctx->screen, "*** evergreen_bind_compute_state\n");
508 rctx->cs_shader_state.shader = (struct r600_pipe_compute *)state;
519 rctx->cs_shader_state.shader = (struct r600_pipe_compute *)state;
536 struct r600_context *rctx = (struct r600_context *)ctx;
537 struct r600_pipe_compute *shader = rctx->cs_shader_state.shader;
587 COMPUTE_DBG(rctx->screen, "input %i : %u\n", i,
596 evergreen_cs_set_vertex_buffer(rctx, 3, 0,
598 evergreen_cs_set_constant_buffer(rctx, 0, 0, input_size,
602 static void evergreen_emit_dispatch(struct r600_context *rctx,
607 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
608 struct r600_pipe_compute *shader = rctx->cs_shader_state.shader;
609 bool render_cond_bit = rctx->b.render_cond && !rctx->b.render_cond_force_off;
611 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
629 COMPUTE_DBG(rctx->screen, "Using %u pipes, "
649 if (rctx->b.gfx_level < CAYMAN) {
676 if (rctx->is_debug)
677 eg_trace_emit(rctx);
680 static void compute_setup_cbs(struct r600_context *rctx)
682 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
687 for (i = 0; i < 8 && i < rctx->framebuffer.state.nr_cbufs; i++) {
688 struct r600_surface *cb = (struct r600_surface*)rctx->framebuffer.state.cbufs[i];
689 unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
718 rctx->compute_cb_target_mask);
721 static void compute_emit_cs(struct r600_context *rctx,
724 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
732 if (radeon_emitted(&rctx->b.dma.cs, 0)) {
733 rctx->b.dma.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
736 r600_update_compressed_resource_state(rctx, true);
738 if (!rctx->cmd_buf_is_compute) {
739 rctx->b.gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
740 rctx->cmd_buf_is_compute = true;
743 if (rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_TGSI||
744 rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_NIR) {
745 if (r600_shader_select(&rctx->b.b, rctx->cs_shader_state.shader->sel, &compute_dirty, false)) {
750 current = rctx->cs_shader_state.shader->sel->current;
752 rctx->cs_shader_state.atom.num_dw = current->command_buffer.num_dw;
753 r600_context_add_resource_size(&rctx->b.b, (struct pipe_resource *)current->bo);
754 r600_set_atom_dirty(rctx, &rctx->cs_shader_state.atom, true);
762 unsigned *data = r600_buffer_map_sync_with_rings(&rctx->b, indirect_resource, PIPE_MAP_READ);
769 rctx->cs_block_grid_sizes[i] = info->block[i];
770 rctx->cs_block_grid_sizes[i + 4] = info->indirect ? indirect_grid[i] : info->grid[i];
772 rctx->cs_block_grid_sizes[3] = rctx->cs_block_grid_sizes[7] = 0;
773 rctx->driver_consts[PIPE_SHADER_COMPUTE].cs_block_grid_size_dirty = true;
775 evergreen_emit_atomic_buffer_setup_count(rctx, current, combined_atomics, &atomic_used_mask);
776 r600_need_cs_space(rctx, 0, true, util_bitcount(atomic_used_mask));
779 eg_setup_buffer_constants(rctx, PIPE_SHADER_COMPUTE);
781 r600_update_driver_const_buffers(rctx, true);
783 evergreen_emit_atomic_buffer_setup(rctx, true, combined_atomics, atomic_used_mask);
789 r600_need_cs_space(rctx, 0, true, 0);
796 r600_emit_command_buffer(cs, &rctx->start_compute_cs_cmd);
799 if (rctx->b.gfx_level == EVERGREEN) {
800 if (rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_TGSI||
801 rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_NIR) {
803 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
808 r600_emit_atom(rctx, &rctx->config_state.atom);
811 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
812 r600_flush_emit(rctx);
814 if (rctx->cs_shader_state.shader->ir_type != PIPE_SHADER_IR_TGSI &&
815 rctx->cs_shader_state.shader->ir_type != PIPE_SHADER_IR_NIR) {
817 compute_setup_cbs(rctx);
820 rctx->cs_vertex_buffer_state.atom.num_dw = 12 * util_bitcount(rctx->cs_vertex_buffer_state.dirty_mask);
821 r600_emit_atom(rctx, &rctx->cs_vertex_buffer_state.atom);
825 rat_mask = evergreen_construct_rat_mask(rctx, &rctx->cb_misc_state, 0);
830 r600_emit_atom(rctx, &rctx->b.render_cond_atom);
833 r600_emit_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom);
836 r600_emit_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom);
839 r600_emit_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom);
842 r600_emit_atom(rctx, &rctx->compute_images.atom);
845 r600_emit_atom(rctx, &rctx->compute_buffers.atom);
848 r600_emit_atom(rctx, &rctx->cs_shader_state.atom);
851 evergreen_emit_dispatch(rctx, info, indirect_grid);
855 rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE |
858 r600_flush_emit(rctx);
859 rctx->b.flags = 0;
861 if (rctx->b.gfx_level >= CAYMAN) {
871 if (rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_TGSI ||
872 rctx->cs_shader_state.shader->ir_type == PIPE_SHADER_IR_NIR)
873 evergreen_emit_atomic_buffer_save(rctx, true, combined_atomics, &atomic_used_mask);
876 COMPUTE_DBG(rctx->screen, "cdw: %i\n", cs->cdw);
878 COMPUTE_DBG(rctx->screen, "%4i : 0x%08X\n", i, cs->buf[i]);
888 void evergreen_emit_cs_shader(struct r600_context *rctx,
894 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
921 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
929 struct r600_context *rctx = (struct r600_context *)ctx;
931 struct r600_pipe_compute *shader = rctx->cs_shader_state.shader;
936 rctx->cs_shader_state.pc = info->pc;
942 rctx->cs_shader_state.pc = 0;
946 COMPUTE_DBG(rctx->screen, "*** evergreen_launch_grid: pc = %u\n", info->pc);
950 compute_emit_cs(rctx, info);
957 struct r600_context *rctx = (struct r600_context *)ctx;
960 COMPUTE_DBG(rctx->screen, "*** evergreen_set_compute_resources: start = %u count = %u\n",
974 evergreen_set_rat(rctx->cs_shader_state.shader, i+1,
980 evergreen_cs_set_vertex_buffer(rctx, vtx_id,
992 struct r600_context *rctx = (struct r600_context *)ctx;
993 struct compute_memory_pool *pool = rctx->screen->global_pool;
998 COMPUTE_DBG(rctx->screen, "*** evergreen_set_global_binding first = %u n = %u\n",
1034 evergreen_set_rat(rctx->cs_shader_state.shader, 0, pool->bo, 0, pool->size_in_dw * 4);
1036 evergreen_cs_set_vertex_buffer(rctx, 1, 0,
1040 evergreen_cs_set_vertex_buffer(rctx, 2, 0,
1041 (struct pipe_resource*)rctx->cs_shader_state.shader->code_bo);
1055 void evergreen_init_atom_start_compute_cs(struct r600_context *rctx)
1057 struct r600_command_buffer *cb = &rctx->start_compute_cs_cmd;
1071 switch (rctx->b.family) {
1120 if (rctx->b.gfx_level < CAYMAN) {
1170 if (rctx->b.gfx_level < CAYMAN) {
1181 if (rctx->b.gfx_level < CAYMAN) {
1222 void evergreen_init_compute_state_functions(struct r600_context *rctx)
1224 rctx->b.b.create_compute_state = evergreen_create_compute_state;
1225 rctx->b.b.delete_compute_state = evergreen_delete_compute_state;
1226 rctx->b.b.bind_compute_state = evergreen_bind_compute_state;
1227 // rctx->context.create_sampler_view = evergreen_compute_create_sampler_view;
1228 rctx->b.b.set_compute_resources = evergreen_set_compute_resources;
1229 rctx->b.b.set_global_binding = evergreen_set_global_binding;
1230 rctx->b.b.launch_grid = evergreen_launch_grid;
1241 struct r600_context *rctx = (struct r600_context*)ctx;
1242 struct compute_memory_pool *pool = rctx->screen->global_pool;
1268 COMPUTE_DBG(rctx->screen, "* r600_compute_global_transfer_map()\n"
1273 COMPUTE_DBG(rctx->screen, "Buffer id = %"PRIi64" offset = "