Lines Matching refs:state
96 struct panfrost_pool_ref state;
258 struct pipe_framebuffer_state *state,
274 for (unsigned i = 0; i < state->nr_cbufs; ++i) {
275 if (state->cbufs[i] && !blend->info[i].no_colour)
285 * to emit the blend descriptors, as well as the fragment renderer state
478 panfrost_batch_add_bo(batch, ss->state.bo, PIPE_SHADER_VERTEX);
480 return ss->state.gpu;
655 /* We need to merge several several partial renderer state descriptors,
669 /* Merge with CSO state and upload */
679 /* Word 8, 9 Misc state */
804 * interactions are dynamic state. Pack only the dynamic state here and OR
1641 panfrost_batch_add_bo(batch, view->state.bo, st);
1643 return view->state.gpu;
1733 so->state = panfrost_pool_take_ref(&ctx->descs, payload.gpu);
1752 panfrost_bo_unreference(view->state.bo);
1789 panfrost_batch_add_bo(batch, view->state.bo, stage);
2857 cfg.state = batch->rsd[PIPE_SHADER_VERTEX];
2917 * 3D state. In particular, it groups the fragment shader descriptor with
2918 * depth/stencil, blend, polygon offset, and multisampling state. These pieces
2919 * of state are dirty tracked independently for the benefit of newer GPUs that
2923 * Obscurely, occlusion queries are included. Occlusion query state is nominally
2925 * early-Z state which is part of the RSD.
2953 * together with the renderer state; the combined renderer state
2973 * state specified with the fragment shader, the whole renderer state
3322 * reasons to disable FPK. The only FPK-related state
3337 cfg.state = batch->rsd[PIPE_SHADER_FRAGMENT];
3442 * state as the position shader for backwards compatible
3976 assert(succ && "must be able to set state for a fresh batch");
4113 cfg.state = batch->rsd[PIPE_SHADER_COMPUTE];
4423 /* A given Gallium blend state can be encoded to the hardware in numerous,
4428 * state, and suitable blend constant)
4433 * fixed-function blend state, if it compiles to any, although the constant
4444 * All of this state is encapsulated in the panfrost_blend_state struct
4524 prepare_shader(struct panfrost_shader_state *state,
4528 void *out = &state->partial_rsd;
4534 state->state = panfrost_pool_take_ref(pool, ptr.gpu);
4539 pan_shader_prepare_rsd(&state->info, state->bin.gpu, &cfg);
4550 if (!state->bin.gpu)
4553 bool vs = (state->info.stage == MESA_SHADER_VERTEX);
4554 bool secondary_enable = (vs && state->info.vs.secondary_enable);
4561 state->state = panfrost_pool_take_ref(pool, ptr.gpu);
4565 cfg.stage = pan_shader_stage(&state->info);
4567 cfg.register_allocation = pan_register_allocation(state->info.work_reg_count);
4568 cfg.binary = state->bin.gpu;
4569 cfg.preload.r48_r63 = (state->info.preload >> 48);
4572 cfg.requires_helper_threads = state->info.contains_barrier;
4580 cfg.stage = pan_shader_stage(&state->info);
4582 cfg.register_allocation = pan_register_allocation(state->info.work_reg_count);
4583 cfg.binary = state->bin.gpu + state->info.vs.no_psiz_offset;
4584 cfg.preload.r48_r63 = (state->info.preload >> 48);
4591 unsigned work_count = state->info.vs.secondary_work_reg_count;
4593 cfg.stage = pan_shader_stage(&state->info);
4596 cfg.binary = state->bin.gpu + state->info.vs.secondary_offset;
4597 cfg.preload.r48_r63 = (state->info.vs.secondary_preload >> 48);
4665 panfrost_bo_unreference(view->state.bo);