Lines Matching refs:ctx
328 panfrost_overdraw_alpha(const struct panfrost_context *ctx, bool zero)
330 const struct panfrost_blend_state *so = ctx->blend;
332 for (unsigned i = 0; i < ctx->pipe_framebuffer.nr_cbufs; ++i) {
335 bool enabled = ctx->pipe_framebuffer.cbufs[i] && info.no_colour;
349 struct panfrost_context *ctx = batch->ctx;
350 const struct panfrost_blend_state *so = ctx->blend;
372 ctx->blend_color.color);
379 cfg.alpha_to_one = ctx->blend->base.alpha_to_one;
400 const struct panfrost_device *dev = pan_device(ctx->base.screen);
402 panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
456 pan_allow_forward_pixel_to_kill(struct panfrost_context *ctx, struct panfrost_shader_state *fs)
461 unsigned rt_mask = ctx->fb_rt_mask;
463 bool blend_reads_dest = (ctx->blend->load_dest_mask & rt_mask);
464 bool alpha_to_coverage = ctx->blend->base.alpha_to_coverage;
475 struct panfrost_shader_state *ss = panfrost_get_shader_state(batch->ctx, stage);
514 panfrost_prepare_fs_state(struct panfrost_context *ctx,
518 struct pipe_rasterizer_state *rast = &ctx->rasterizer->base;
519 const struct panfrost_zsa_state *zsa = ctx->depth_stencil;
520 struct panfrost_shader_state *fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
521 struct panfrost_blend_state *so = ctx->blend;
522 bool alpha_to_coverage = ctx->blend->base.alpha_to_coverage;
525 unsigned rt_count = ctx->pipe_framebuffer.nr_cbufs;
532 bool has_oq = ctx->occlusion_query && ctx->active_queries;
535 if (panfrost_fs_required(fs, so, &ctx->pipe_framebuffer, zsa)) {
539 ctx->depth_stencil->writes_zs ||
541 ctx->blend->base.alpha_to_coverage,
542 ctx->depth_stencil->zs_always_passes);
548 pan_allow_forward_pixel_to_kill(ctx, fs);
576 cfg.stencil_mask_misc.srgb = util_format_is_srgb(ctx->pipe_framebuffer.cbufs[0]->format);
585 ctx->blend_color.color);
603 cfg.multisample_misc.sample_mask = msaa ? ctx->sample_mask : 0xFFFF;
606 msaa && (ctx->min_samples > 1);
626 cfg.multisample_misc.overdraw_alpha0 = panfrost_overdraw_alpha(ctx, 0);
627 cfg.multisample_misc.overdraw_alpha1 = panfrost_overdraw_alpha(ctx, 1);
635 cfg.stencil_front.reference_value = ctx->stencil_ref.ref_value[0];
636 cfg.stencil_back.reference_value = ctx->stencil_ref.ref_value[back_enab ? 1 : 0];
646 panfrost_emit_frag_shader(struct panfrost_context *ctx,
650 const struct panfrost_zsa_state *zsa = ctx->depth_stencil;
651 const struct panfrost_rasterizer *rast = ctx->rasterizer;
653 panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
659 panfrost_prepare_fs_state(ctx, blend_shaders, &rsd);
662 if (ctx->pipe_framebuffer.nr_cbufs > 0 && !blend_shaders[0]) {
665 rsd.opaque[14] = ctx->blend->equation[0];
670 if (panfrost_fs_required(fs, ctx->blend, &ctx->pipe_framebuffer, zsa)) {
696 struct panfrost_context *ctx = batch->ctx;
697 struct panfrost_shader_state *ss = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
706 unsigned rt_count = MAX2(ctx->pipe_framebuffer.nr_cbufs, 1);
716 panfrost_emit_frag_shader(ctx, (struct mali_renderer_state_packed *) xfer.cpu, blend_shaders);
729 struct panfrost_context *ctx = batch->ctx;
730 const struct pipe_viewport_state *vp = &ctx->pipe_viewport;
731 const struct pipe_scissor_state *ss = &ctx->scissor;
732 const struct pipe_rasterizer_state *rast = &ctx->rasterizer->base;
810 struct panfrost_context *ctx = batch->ctx;
811 const struct panfrost_zsa_state *zsa = ctx->depth_stencil;
812 struct panfrost_rasterizer *rast = ctx->rasterizer;
813 struct panfrost_shader_state *fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
820 cfg.front_reference_value = ctx->stencil_ref.ref_value[0];
821 cfg.back_reference_value = ctx->stencil_ref.ref_value[back_enab ? 1 : 0];
860 batch->ctx->valhall_has_blend_shader = has_blend_shader;
871 struct panfrost_context *ctx = batch->ctx;
872 unsigned buffer_count = util_last_bit(ctx->vb_mask);
877 u_foreach_bit(i, ctx->vb_mask) {
878 struct pipe_vertex_buffer vb = ctx->vertex_buffers[i];
905 struct panfrost_context *ctx = batch->ctx;
906 struct panfrost_vertex_state *vtx = ctx->vertex;
917 cfg.stride = ctx->vertex_buffers[vbi].stride;
968 struct panfrost_context *ctx = batch->ctx;
969 unsigned last_bit = util_last_bit(ctx->image_mask[stage]);
977 struct pipe_image_view *image = &ctx->images[stage][i];
979 if (!(ctx->image_mask[stage] & BITFIELD_BIT(i))) {
1006 panfrost_update_sampler_view(&view, &ctx->base);
1054 struct panfrost_context *ctx = batch->ctx;
1055 const struct pipe_viewport_state *vp = &ctx->pipe_viewport;
1066 struct panfrost_context *ctx = batch->ctx;
1067 const struct pipe_viewport_state *vp = &ctx->pipe_viewport;
1079 struct panfrost_context *ctx = batch->ctx;
1083 struct pipe_sampler_view *tex = &ctx->sampler_views[st][texidx]->base;
1123 struct panfrost_context *ctx = batch->ctx;
1130 struct pipe_image_view *image = &ctx->images[st][idx];
1159 struct panfrost_context *ctx = batch->ctx;
1161 assert(ctx->ssbo_mask[st] & (1 << ssbo_id));
1162 struct pipe_shader_buffer sb = ctx->ssbo[st][ssbo_id];
1184 struct panfrost_context *ctx = batch->ctx;
1185 struct pipe_sampler_state *sampl = &ctx->samplers[st][samp_idx]->base;
1204 struct panfrost_context *ctx = batch->ctx;
1206 uniform->u[0] = ctx->compute_grid->grid[0];
1207 uniform->u[1] = ctx->compute_grid->grid[1];
1208 uniform->u[2] = ctx->compute_grid->grid[2];
1215 struct panfrost_context *ctx = batch->ctx;
1217 uniform->u[0] = ctx->compute_grid->block[0];
1218 uniform->u[1] = ctx->compute_grid->block[1];
1219 uniform->u[2] = ctx->compute_grid->block[2];
1226 struct panfrost_context *ctx = batch->ctx;
1228 uniform->u[0] = ctx->compute_grid->work_dim;
1239 struct panfrost_context *ctx = batch->ctx;
1240 struct panfrost_device *dev = pan_device(ctx->base.screen);
1259 struct panfrost_context *ctx = batch->ctx;
1260 struct panfrost_device *dev = pan_device(ctx->base.screen);
1316 panfrost_get_shader_state(batch->ctx, PIPE_SHADER_VERTEX);
1321 if (buf < batch->ctx->streamout.num_targets)
1322 target = batch->ctx->streamout.targets[buf];
1343 uniforms[i].u[0] = batch->ctx->vertex_count;
1387 batch->ctx->first_vertex_sysval_ptr =
1389 batch->ctx->base_vertex_sysval_ptr =
1390 batch->ctx->first_vertex_sysval_ptr + 4;
1391 batch->ctx->base_instance_sysval_ptr =
1392 batch->ctx->first_vertex_sysval_ptr + 8;
1394 uniforms[i].u[0] = batch->ctx->offset_start;
1395 uniforms[i].u[1] = batch->ctx->base_vertex;
1396 uniforms[i].u[2] = batch->ctx->base_instance;
1399 uniforms[i].u[0] = batch->ctx->drawid;
1408 panfrost_map_constant_buffer_cpu(struct panfrost_context *ctx,
1417 panfrost_flush_writer(ctx, rsrc, "CPU constant buffer mapping");
1463 struct panfrost_context *ctx = batch->ctx;
1464 struct panfrost_shader_variants *all = ctx->shader[stage];
1469 struct panfrost_constant_buffer *buf = &ctx->constant_buffer[stage];
1481 struct panfrost_shader_state *shader = panfrost_get_shader_state(ctx, stage);
1545 batch->ctx->first_vertex_sysval_ptr = ptr;
1548 batch->ctx->base_vertex_sysval_ptr = ptr;
1551 batch->ctx->base_instance_sysval_ptr = ptr;
1575 panfrost_map_constant_buffer_cpu(ctx, buf, src.ubo);
1588 struct panfrost_context *ctx = batch->ctx;
1589 struct panfrost_device *dev = pan_device(ctx->base.screen);
1590 struct panfrost_shader_variants *all = ctx->shader[PIPE_SHADER_COMPUTE];
1653 struct panfrost_context *ctx = pan_context(pctx);
1731 struct panfrost_pool *pool = so->pool ?: &ctx->descs;
1733 so->state = panfrost_pool_take_ref(&ctx->descs, payload.gpu);
1761 struct panfrost_context *ctx = batch->ctx;
1763 if (!ctx->sampler_view_count[stage])
1769 ctx->sampler_view_count[stage],
1774 for (int i = 0; i < ctx->sampler_view_count[stage]; ++i) {
1775 struct panfrost_sampler_view *view = ctx->sampler_views[stage][i];
1785 panfrost_update_sampler_view(view, &ctx->base);
1796 for (int i = 0; i < ctx->sampler_view_count[stage]; ++i) {
1797 struct panfrost_sampler_view *view = ctx->sampler_views[stage][i];
1804 panfrost_update_sampler_view(view, &ctx->base);
1811 ctx->sampler_view_count[stage],
1820 struct panfrost_context *ctx = batch->ctx;
1822 if (!ctx->sampler_count[stage])
1827 ctx->sampler_count[stage],
1831 for (unsigned i = 0; i < ctx->sampler_count[stage]; ++i) {
1832 struct panfrost_sampler_state *st = ctx->samplers[stage][i];
1845 emit_image_attribs(struct panfrost_context *ctx, enum pipe_shader_type shader,
1848 struct panfrost_device *dev = pan_device(ctx->base.screen);
1849 unsigned last_bit = util_last_bit(ctx->image_mask[shader]);
1852 enum pipe_format format = ctx->images[shader][i].format;
1881 struct panfrost_context *ctx = batch->ctx;
1882 unsigned last_bit = util_last_bit(ctx->image_mask[shader]);
1885 struct pipe_image_view *image = &ctx->images[shader][i];
1887 if (!(ctx->image_mask[shader] & (1 << i)) ||
1954 struct panfrost_context *ctx = batch->ctx;
1955 struct panfrost_shader_state *shader = panfrost_get_shader_state(ctx, type);
1972 emit_image_attribs(ctx, type, attribs.cpu, 0);
1989 struct panfrost_context *ctx = batch->ctx;
1990 struct panfrost_vertex_state *so = ctx->vertex;
1991 struct panfrost_shader_state *vs = panfrost_get_shader_state(ctx, PIPE_SHADER_VERTEX);
1992 bool instanced = ctx->indirect_draw || ctx->instance_count > 1;
1993 uint32_t image_mask = ctx->image_mask[PIPE_SHADER_VERTEX];
2043 if (!(ctx->vb_mask & (1 << vbi)))
2046 struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[vbi];
2068 if (ctx->indirect_draw) {
2094 unsigned hw_divisor = ctx->padded_count * divisor;
2096 if (ctx->instance_count <= 1) {
2112 cfg.divisor = ctx->padded_count;
2157 panfrost_vertex_id(ctx->padded_count, &bufs[k], ctx->instance_count > 1);
2164 panfrost_instance_id(ctx->padded_count, &bufs[k], ctx->instance_count > 1);
2175 emit_image_attribs(ctx, PIPE_SHADER_VERTEX, out + so->num_elements, k);
2177 k += (util_last_bit(ctx->image_mask[PIPE_SHADER_VERTEX]) * 2);
2201 struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[vbi];
2208 if (ctx->base_instance && so->pipe[i].instance_divisor) {
2209 src_offset += (ctx->base_instance * buf->stride) /
2216 if (so->pipe[i].instance_divisor && ctx->instance_count > 1)
2217 src_offset -= buf->stride * ctx->offset_start;
2237 batch->ctx->indirect_draw ? 0 :
2543 struct panfrost_context *ctx = batch->ctx;
2546 vs = panfrost_get_shader_state(ctx, PIPE_SHADER_VERTEX);
2547 fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
2554 point_coord_mask = ctx->rasterizer->base.sprite_coord_enable;
2570 prelink ? &ctx->descs : &batch->pool;
2638 struct panfrost_context *ctx = batch->ctx;
2646 ctx->indirect_draw ?
2659 struct panfrost_device *dev = pan_device(batch->ctx->base.screen);
2686 struct panfrost_device *dev = pan_device(batch->ctx->base.screen);
2794 struct panfrost_context *ctx,
2798 if (!ctx->active_queries)
2802 ctx->prims_generated += prims;
2804 if (!ctx->streamout.num_targets)
2807 ctx->tf_prims_generated += prims;
2808 ctx->dirty |= PAN_DIRTY_SO;
2812 panfrost_update_streamout_offsets(struct panfrost_context *ctx)
2814 unsigned count = u_stream_outputs_for_vertices(ctx->active_prim,
2815 ctx->vertex_count);
2817 for (unsigned i = 0; i < ctx->streamout.num_targets; ++i) {
2818 if (!ctx->streamout.targets[i])
2821 pan_so_target(ctx->streamout.targets[i])->offset += count;
2840 d->offset_start = batch->ctx->offset_start;
2841 d->instance_size = batch->ctx->instance_count > 1 ?
2842 batch->ctx->padded_count : 1;
2890 panfrost_emit_primitive_size(struct panfrost_context *ctx,
2894 struct panfrost_rasterizer *rast = ctx->rasterizer;
2897 if (panfrost_writes_point_size(ctx)) {
2935 struct panfrost_context *ctx = batch->ctx;
2936 struct panfrost_shader_state *ss = panfrost_get_shader_state(ctx, st);
2939 unsigned dirty_3d = ctx->dirty;
2940 unsigned dirty = ctx->dirty_shader[st];
2992 struct panfrost_context *ctx = batch->ctx;
2993 unsigned dirty = ctx->dirty;
3006 (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & PAN_DIRTY_STAGE_SHADER))
3026 struct panfrost_device *dev = pan_device(batch->ctx->base.screen);
3056 panfrost_emit_primitive(struct panfrost_context *ctx,
3061 UNUSED struct pipe_rasterizer_state *rast = &ctx->rasterizer->base;
3069 if (panfrost_writes_point_size(ctx))
3092 panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
3101 cfg.index_count = ctx->indirect_draw ? 1 : draw->count;
3119 cfg.base_vertex_offset = draw->index_bias - ctx->offset_start;
3138 struct panfrost_context *ctx = batch->ctx;
3152 ctx->sampler_view_count[stage]);
3156 ctx->sampler_count[stage]);
3160 util_last_bit(ctx->image_mask[stage]));
3165 ctx->vertex->num_elements);
3169 util_last_bit(ctx->vb_mask));
3206 struct panfrost_context *ctx = batch->ctx;
3207 struct pipe_rasterizer_state *rast = &ctx->rasterizer->base;
3223 if (ctx->occlusion_query && ctx->active_queries) {
3224 if (ctx->occlusion_query->type == PIPE_QUERY_OCCLUSION_COUNTER)
3229 struct panfrost_resource *rsrc = pan_resource(ctx->occlusion_query->rsrc);
3231 panfrost_batch_write_rsrc(ctx->batch, rsrc,
3237 panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
3240 cfg.sample_mask = rast->multisample ? ctx->sample_mask : 0xFFFF;
3249 ((ctx->min_samples > 1) || ctx->valhall_has_blend_shader));
3261 bool has_oq = ctx->occlusion_query && ctx->active_queries;
3265 ctx->depth_stencil->writes_zs || has_oq,
3266 ctx->blend->base.alpha_to_coverage,
3267 ctx->depth_stencil->zs_always_passes);
3272 cfg.allow_forward_pixel_to_kill = pan_allow_forward_pixel_to_kill(ctx, fs);
3286 ctx->fb_rt_mask;
3297 ctx->blend->base.alpha_to_coverage;
3306 cfg.alpha_to_coverage = ctx->blend->base.alpha_to_coverage;
3308 cfg.overdraw_alpha0 = panfrost_overdraw_alpha(ctx, 0);
3309 cfg.overdraw_alpha1 = panfrost_overdraw_alpha(ctx, 1);
3368 struct panfrost_context *ctx = batch->ctx;
3371 panfrost_get_shader_state(ctx, PIPE_SHADER_VERTEX);
3374 panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT);
3376 bool fs_required = panfrost_fs_required(fs, ctx->blend,
3377 &ctx->pipe_framebuffer,
3378 ctx->depth_stencil);
3385 panfrost_emit_primitive(ctx, info, draw, 0, secondary_shader,
3418 panfrost_emit_primitive_size(ctx, info->mode == PIPE_PRIM_POINTS, 0,
3466 struct panfrost_context *ctx = batch->ctx;
3471 panfrost_emit_primitive(ctx, info, draw, indices, secondary_shader,
3488 panfrost_emit_primitive_size(ctx, prim == PIPE_PRIM_POINTS, psiz, prim_size);
3498 struct panfrost_context *ctx = batch->ctx;
3504 if (batch->ctx->streamout.num_targets == 0)
3514 struct panfrost_shader_state *vs = panfrost_get_shader_state(ctx, PIPE_SHADER_VERTEX);
3519 struct panfrost_shader_variants *saved_vs = ctx->shader[PIPE_SHADER_VERTEX];
3524 ctx->shader[PIPE_SHADER_VERTEX] = &v;
3542 cfg.compute.attribute_offset = batch->ctx->offset_start;
3572 ctx->shader[PIPE_SHADER_VERTEX] = saved_vs;
3587 struct panfrost_context *ctx = batch->ctx;
3594 if ((ctx->dirty & PAN_DIRTY_RASTERIZER) ||
3595 ((ctx->active_prim == PIPE_PRIM_POINTS) ^
3598 ctx->active_prim = info->mode;
3599 panfrost_update_shader_variant(ctx, PIPE_SHADER_FRAGMENT);
3603 ctx->indirect_draw = false;
3604 ctx->vertex_count = draw->count + (info->index_size ? abs(draw->index_bias) : 0);
3605 ctx->instance_count = info->instance_count;
3606 ctx->base_vertex = info->index_size ? draw->index_bias : 0;
3607 ctx->base_instance = info->start_instance;
3608 ctx->active_prim = info->mode;
3609 ctx->drawid = drawid_offset;
3611 struct panfrost_shader_state *vs = panfrost_get_shader_state(ctx, PIPE_SHADER_VERTEX);
3631 unsigned vertex_count = ctx->vertex_count;
3645 ctx->offset_start = min_index + draw->index_bias;
3647 ctx->offset_start = draw->start;
3661 ctx->padded_count = panfrost_padded_vertex_count(count);
3663 ctx->padded_count = vertex_count;
3665 panfrost_statistics_record(ctx, info, draw);
3689 ctx->padded_count *
3690 ctx->instance_count,
3702 panfrost_clean_state_3d(ctx);
3712 panfrost_update_streamout_offsets(ctx);
3764 struct panfrost_context *ctx = batch->ctx;
3765 struct panfrost_device *dev = pan_device(ctx->base.screen);
3769 assert(ctx->streamout.num_targets == 0);
3771 ctx->active_prim = info->mode;
3772 ctx->drawid = drawid_offset;
3773 ctx->indirect_draw = true;
3775 struct panfrost_shader_state *vs = panfrost_get_shader_state(ctx, PIPE_SHADER_VERTEX);
3808 ctx->instance_count = ctx->vertex_count = ctx->padded_count = 0;
3809 ctx->offset_start = 0;
3814 ctx->first_vertex_sysval_ptr = 0;
3815 ctx->base_vertex_sysval_ptr = 0;
3816 ctx->base_instance_sysval_ptr = 0;
3821 panfrost_clean_state_3d(ctx);
3867 util_bitcount(ctx->image_mask[PIPE_SHADER_VERTEX]);
3875 .first_vertex_sysval = ctx->first_vertex_sysval_ptr,
3876 .base_vertex_sysval = ctx->base_vertex_sysval_ptr,
3877 .base_instance_sysval = ctx->base_instance_sysval_ptr,
3887 if (panfrost_writes_point_size(ctx))
3925 struct panfrost_context *ctx = batch->ctx;
3926 struct pipe_rasterizer_state *rast = &ctx->rasterizer->base;
3948 struct panfrost_context *ctx = pan_context(pipe);
3951 if (!panfrost_render_condition_check(ctx))
3962 struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
3968 batch = panfrost_get_fresh_batch_for_fbo(ctx, "Too many draws");
3973 batch = panfrost_get_fresh_batch_for_fbo(ctx, "State change");
3983 if (ctx->dirty & (PAN_DIRTY_VIEWPORT | PAN_DIRTY_SCISSOR))
3988 panfrost_dirty_state_all(ctx);
3991 ctx->dirty |= PAN_DIRTY_PARAMS | PAN_DIRTY_DRAWID;
4022 ctx->dirty |= PAN_DIRTY_DRAWID;
4037 struct panfrost_context *ctx = pan_context(pipe);
4041 panfrost_flush_all_batches(ctx, "Launch grid pre-barrier");
4043 struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
4046 &ctx->shader[PIPE_SHADER_COMPUTE]->variants[0];
4071 ctx->compute_grid = info;
4082 .buffer_size = ctx->shader[PIPE_SHADER_COMPUTE]->req_input_mem,
4164 panfrost_flush_all_batches(ctx, "Launch grid post-barrier");
4406 struct panfrost_context *ctx = pan_context(pctx);
4409 pan_legalize_afbc_format(ctx, pan_resource(texture), template->format);
4695 struct panfrost_device *dev = pan_device(batch->ctx->base.screen);