Lines Matching refs:batch
289 panfrost_get_blend_shaders(struct panfrost_batch *batch,
295 for (unsigned c = 0; c < batch->key.nr_cbufs; ++c) {
296 if (batch->key.cbufs[c]) {
297 blend_shaders[c] = panfrost_get_blend(batch,
346 panfrost_emit_blend(struct panfrost_batch *batch, void *rts, mali_ptr *blend_shaders)
348 unsigned rt_count = batch->key.nr_cbufs;
349 struct panfrost_context *ctx = batch->ctx;
358 if (rt_count == 0 || !batch->key.cbufs[i] || so->info[i].no_colour) {
370 enum pipe_format format = batch->key.cbufs[i]->format;
473 panfrost_emit_compute_shader_meta(struct panfrost_batch *batch, enum pipe_shader_type stage)
475 struct panfrost_shader_state *ss = panfrost_get_shader_state(batch->ctx, stage);
477 panfrost_batch_add_bo(batch, ss->bin.bo, PIPE_SHADER_VERTEX);
478 panfrost_batch_add_bo(batch, ss->state.bo, PIPE_SHADER_VERTEX);
694 panfrost_emit_frag_shader_meta(struct panfrost_batch *batch)
696 struct panfrost_context *ctx = batch->ctx;
699 panfrost_batch_add_bo(batch, ss->bin.bo, PIPE_SHADER_FRAGMENT);
704 xfer = pan_pool_alloc_desc(&batch->pool.base, RENDERER_STATE);
708 xfer = pan_pool_alloc_desc_aggregate(&batch->pool.base,
714 panfrost_get_blend_shaders(batch, blend_shaders);
719 panfrost_emit_blend(batch, xfer.cpu + pan_size(RENDERER_STATE), blend_shaders);
727 panfrost_emit_viewport(struct panfrost_batch *batch)
729 struct panfrost_context *ctx = batch->ctx;
747 unsigned minx = MIN2(batch->key.width, MAX2((int) vp_minx, 0));
748 unsigned maxx = MIN2(batch->key.width, MAX2((int) vp_maxx, 0));
749 unsigned miny = MIN2(batch->key.height, MAX2((int) vp_miny, 0));
750 unsigned maxy = MIN2(batch->key.height, MAX2((int) vp_maxy, 0));
763 panfrost_batch_union_scissor(batch, minx, miny, maxx, maxy);
764 batch->scissor_culls_everything = (minx >= maxx || miny >= maxy);
770 batch->minimum_z = rast->depth_clip_near ? minz : -INFINITY;
771 batch->maximum_z = rast->depth_clip_far ? maxz : +INFINITY;
774 struct panfrost_ptr T = pan_pool_alloc_desc(&batch->pool.base, VIEWPORT);
782 cfg.minimum_z = batch->minimum_z;
783 cfg.maximum_z = batch->maximum_z;
788 pan_pack(&batch->scissor, SCISSOR, cfg) {
808 panfrost_emit_depth_stencil(struct panfrost_batch *batch)
810 struct panfrost_context *ctx = batch->ctx;
816 struct panfrost_ptr T = pan_pool_alloc_desc(&batch->pool.base, DEPTH_STENCIL);
843 panfrost_emit_blend_valhall(struct panfrost_batch *batch)
845 unsigned rt_count = MAX2(batch->key.nr_cbufs, 1);
847 struct panfrost_ptr T = pan_pool_alloc_desc_array(&batch->pool.base, rt_count, BLEND);
850 panfrost_get_blend_shaders(batch, blend_shaders);
852 panfrost_emit_blend(batch, T.cpu, blend_shaders);
860 batch->ctx->valhall_has_blend_shader = has_blend_shader;
869 panfrost_emit_vertex_buffers(struct panfrost_batch *batch)
871 struct panfrost_context *ctx = batch->ctx;
873 struct panfrost_ptr T = pan_pool_alloc_desc_array(&batch->pool.base,
883 panfrost_batch_read_rsrc(batch, rsrc, PIPE_SHADER_VERTEX);
903 panfrost_emit_vertex_data(struct panfrost_batch *batch)
905 struct panfrost_context *ctx = batch->ctx;
907 struct panfrost_ptr T = pan_pool_alloc_desc_array(&batch->pool.base,
966 panfrost_emit_images(struct panfrost_batch *batch, enum pipe_shader_type stage)
968 struct panfrost_context *ctx = batch->ctx;
972 pan_pool_alloc_desc_array(&batch->pool.base, last_bit, TEXTURE);
987 * Use the batch pool for a transient allocation, rather than
992 .pool = &batch->pool
1009 panfrost_track_image_access(batch, stage, image);
1017 panfrost_map_constant_buffer_gpu(struct panfrost_batch *batch,
1026 panfrost_batch_read_rsrc(batch, rsrc, st);
1032 return pan_pool_upload_aligned(&batch->pool.base,
1051 panfrost_upload_viewport_scale_sysval(struct panfrost_batch *batch,
1054 struct panfrost_context *ctx = batch->ctx;
1063 panfrost_upload_viewport_offset_sysval(struct panfrost_batch *batch,
1066 struct panfrost_context *ctx = batch->ctx;
1074 static void panfrost_upload_txs_sysval(struct panfrost_batch *batch,
1079 struct panfrost_context *ctx = batch->ctx;
1118 static void panfrost_upload_image_size_sysval(struct panfrost_batch *batch,
1123 struct panfrost_context *ctx = batch->ctx;
1154 panfrost_upload_ssbo_sysval(struct panfrost_batch *batch,
1159 struct panfrost_context *ctx = batch->ctx;
1168 panfrost_batch_write_rsrc(batch, rsrc, st);
1179 panfrost_upload_sampler_sysval(struct panfrost_batch *batch,
1184 struct panfrost_context *ctx = batch->ctx;
1201 panfrost_upload_num_work_groups_sysval(struct panfrost_batch *batch,
1204 struct panfrost_context *ctx = batch->ctx;
1212 panfrost_upload_local_group_size_sysval(struct panfrost_batch *batch,
1215 struct panfrost_context *ctx = batch->ctx;
1223 panfrost_upload_work_dim_sysval(struct panfrost_batch *batch,
1226 struct panfrost_context *ctx = batch->ctx;
1236 panfrost_upload_sample_positions_sysval(struct panfrost_batch *batch,
1239 struct panfrost_context *ctx = batch->ctx;
1242 unsigned samples = util_framebuffer_get_num_samples(&batch->key);
1247 panfrost_upload_multisampled_sysval(struct panfrost_batch *batch,
1250 unsigned samples = util_framebuffer_get_num_samples(&batch->key);
1256 panfrost_upload_rt_conversion_sysval(struct panfrost_batch *batch,
1259 struct panfrost_context *ctx = batch->ctx;
1264 if (rt < batch->key.nr_cbufs && batch->key.cbufs[rt]) {
1265 enum pipe_format format = batch->key.cbufs[rt]->format;
1282 panfrost_upload_sysvals(struct panfrost_batch *batch,
1294 panfrost_upload_viewport_scale_sysval(batch,
1298 panfrost_upload_viewport_offset_sysval(batch,
1302 panfrost_upload_txs_sysval(batch, st,
1307 panfrost_upload_ssbo_sysval(batch, st,
1316 panfrost_get_shader_state(batch->ctx, PIPE_SHADER_VERTEX);
1321 if (buf < batch->ctx->streamout.num_targets)
1322 target = batch->ctx->streamout.targets[buf];
1336 panfrost_batch_write_rsrc(batch, rsrc, PIPE_SHADER_VERTEX);
1343 uniforms[i].u[0] = batch->ctx->vertex_count;
1348 batch->num_wg_sysval[j] =
1351 panfrost_upload_num_work_groups_sysval(batch,
1355 panfrost_upload_local_group_size_sysval(batch,
1359 panfrost_upload_work_dim_sysval(batch,
1363 panfrost_upload_sampler_sysval(batch, st,
1368 panfrost_upload_image_size_sysval(batch, st,
1373 panfrost_upload_sample_positions_sysval(batch,
1377 panfrost_upload_multisampled_sysval(batch,
1382 panfrost_upload_rt_conversion_sysval(batch,
1387 batch->ctx->first_vertex_sysval_ptr =
1389 batch->ctx->base_vertex_sysval_ptr =
1390 batch->ctx->first_vertex_sysval_ptr + 4;
1391 batch->ctx->base_instance_sysval_ptr =
1392 batch->ctx->first_vertex_sysval_ptr + 8;
1394 uniforms[i].u[0] = batch->ctx->offset_start;
1395 uniforms[i].u[1] = batch->ctx->base_vertex;
1396 uniforms[i].u[2] = batch->ctx->base_instance;
1399 uniforms[i].u[0] = batch->ctx->drawid;
1457 panfrost_emit_const_buf(struct panfrost_batch *batch,
1463 struct panfrost_context *ctx = batch->ctx;
1475 pan_pool_alloc_aligned(&batch->pool.base, sys_size, 16);
1478 panfrost_upload_sysvals(batch, &transfer, ss, stage);
1487 ubos = pan_pool_alloc_desc_array(&batch->pool.base,
1491 ubos = pan_pool_alloc_desc_array(&batch->pool.base,
1511 address = panfrost_map_constant_buffer_gpu(batch,
1526 pan_pool_alloc_aligned(&batch->pool.base,
1545 batch->ctx->first_vertex_sysval_ptr = ptr;
1548 batch->ctx->base_vertex_sysval_ptr = ptr;
1551 batch->ctx->base_instance_sysval_ptr = ptr;
1562 batch->num_wg_sysval[sysval_comp] = ptr;
1585 panfrost_emit_shared_memory(struct panfrost_batch *batch,
1588 struct panfrost_context *ctx = batch->ctx;
1593 pan_pool_alloc_desc(&batch->pool.base, LOCAL_STORAGE);
1605 panfrost_batch_get_scratchpad(batch,
1619 panfrost_batch_get_shared_memory(batch, size, 1);
1630 panfrost_get_tex_desc(struct panfrost_batch *batch,
1640 panfrost_batch_read_rsrc(batch, rsrc, st);
1641 panfrost_batch_add_bo(batch, view->state.bo, st);
1758 panfrost_emit_texture_descriptors(struct panfrost_batch *batch,
1761 struct panfrost_context *ctx = batch->ctx;
1768 pan_pool_alloc_desc_array(&batch->pool.base,
1788 panfrost_batch_read_rsrc(batch, rsrc, stage);
1789 panfrost_batch_add_bo(batch, view->state.bo, stage);
1806 trampolines[i] = panfrost_get_tex_desc(batch, stage, view);
1809 return pan_pool_upload_aligned(&batch->pool.base, trampolines,
1817 panfrost_emit_sampler_descriptors(struct panfrost_batch *batch,
1820 struct panfrost_context *ctx = batch->ctx;
1826 pan_pool_alloc_desc_array(&batch->pool.base,
1877 emit_image_bufs(struct panfrost_batch *batch, enum pipe_shader_type shader,
1881 struct panfrost_context *ctx = batch->ctx;
1909 panfrost_track_image_access(batch, shader, image);
1950 panfrost_emit_image_attribs(struct panfrost_batch *batch,
1954 struct panfrost_context *ctx = batch->ctx;
1967 pan_pool_alloc_desc_array(&batch->pool.base, buf_count, ATTRIBUTE_BUFFER);
1970 pan_pool_alloc_desc_array(&batch->pool.base, attr_count, ATTRIBUTE);
1973 emit_image_bufs(batch, type, bufs.cpu, 0);
1986 panfrost_emit_vertex_data(struct panfrost_batch *batch,
1989 struct panfrost_context *ctx = batch->ctx;
2023 pan_pool_alloc_desc_array(&batch->pool.base, nr_bufs,
2026 pan_pool_alloc_desc_array(&batch->pool.base, count,
2053 panfrost_batch_read_rsrc(batch, rsrc, PIPE_SHADER_VERTEX);
2176 emit_image_bufs(batch, PIPE_SHADER_VERTEX, bufs + k, k);
2231 panfrost_emit_varyings(struct panfrost_batch *batch,
2237 batch->ctx->indirect_draw ? 0 :
2238 pan_pool_alloc_aligned(&batch->invisible_pool.base, size, 64).gpu;
2532 panfrost_emit_varying_descriptor(struct panfrost_batch *batch,
2543 struct panfrost_context *ctx = batch->ctx;
2570 prelink ? &ctx->descs : &batch->pool;
2578 pan_pool_alloc_desc_array(&batch->pool.base,
2593 panfrost_emit_varyings(batch,
2604 *position = panfrost_emit_varyings(batch,
2609 *psiz = panfrost_emit_varyings(batch,
2634 panfrost_emit_vertex_tiler_jobs(struct panfrost_batch *batch,
2638 struct panfrost_context *ctx = batch->ctx;
2644 unsigned vertex = panfrost_add_job(&batch->pool.base, &batch->scoreboard,
2647 batch->indirect_draw_job_id : 0,
2650 panfrost_add_job(&batch->pool.base, &batch->scoreboard,
2657 emit_tls(struct panfrost_batch *batch)
2659 struct panfrost_device *dev = pan_device(batch->ctx->base.screen);
2662 if (PAN_ARCH <= 5 && batch->framebuffer.gpu)
2666 batch->stack_size ?
2667 panfrost_batch_get_scratchpad(batch,
2668 batch->stack_size,
2675 .size = batch->stack_size,
2679 assert(batch->tls.cpu);
2680 GENX(pan_emit_tls)(&tls, batch->tls.cpu);
2684 emit_fbd(struct panfrost_batch *batch, const struct pan_fb_info *fb)
2686 struct panfrost_device *dev = pan_device(batch->ctx->base.screen);
2688 batch->stack_size ?
2689 panfrost_batch_get_scratchpad(batch,
2690 batch->stack_size,
2697 .size = batch->stack_size,
2701 batch->framebuffer.gpu |=
2702 GENX(pan_emit_fbd)(dev, fb, &tls, &batch->tiler_ctx,
2703 batch->framebuffer.cpu);
2709 panfrost_initialize_surface(struct panfrost_batch *batch,
2722 emit_fragment_job(struct panfrost_batch *batch, const struct pan_fb_info *pfb)
2725 * Also, add the surfaces we're writing to to the batch */
2727 struct pipe_framebuffer_state *fb = &batch->key;
2730 panfrost_initialize_surface(batch, fb->cbufs[i]);
2732 panfrost_initialize_surface(batch, fb->zsbuf);
2745 batch->maxx = MIN2(batch->maxx, fb->width);
2746 batch->maxy = MIN2(batch->maxy, fb->height);
2751 assert(batch->maxx > batch->minx);
2752 assert(batch->maxy > batch->miny);
2755 pan_pool_alloc_desc(&batch->pool.base, FRAGMENT_JOB);
2757 GENX(pan_emit_fragment_job)(pfb, batch->framebuffer.gpu,
2837 pan_emit_draw_descs(struct panfrost_batch *batch,
2840 d->offset_start = batch->ctx->offset_start;
2841 d->instance_size = batch->ctx->instance_count > 1 ?
2842 batch->ctx->padded_count : 1;
2844 d->uniform_buffers = batch->uniform_buffers[st];
2845 d->push_uniforms = batch->push_uniforms[st];
2846 d->textures = batch->textures[st];
2847 d->samplers = batch->samplers[st];
2851 panfrost_draw_emit_vertex_section(struct panfrost_batch *batch,
2857 cfg.state = batch->rsd[PIPE_SHADER_VERTEX];
2862 cfg.thread_storage = batch->tls.gpu;
2863 pan_emit_draw_descs(batch, &cfg, PIPE_SHADER_VERTEX);
2868 panfrost_draw_emit_vertex(struct panfrost_batch *batch,
2884 panfrost_draw_emit_vertex_section(batch, vs_vary, varyings,
2932 panfrost_update_shader_state(struct panfrost_batch *batch,
2935 struct panfrost_context *ctx = batch->ctx;
2943 batch->textures[st] =
2944 panfrost_emit_texture_descriptors(batch, st);
2948 batch->samplers[st] =
2949 panfrost_emit_sampler_descriptors(batch, st);
2958 batch->rsd[st] = panfrost_emit_compute_shader_meta(batch, st);
2963 batch->images[st] = panfrost_emit_images(batch, st);
2967 batch->uniform_buffers[st] = panfrost_emit_const_buf(batch, st,
2968 NULL, &batch->push_uniforms[st], NULL);
2979 batch->rsd[st] = panfrost_emit_frag_shader_meta(batch);
2983 batch->attribs[st] = panfrost_emit_image_attribs(batch,
2984 &batch->attrib_bufs[st], st);
2990 panfrost_update_state_3d(struct panfrost_batch *batch)
2992 struct panfrost_context *ctx = batch->ctx;
2996 panfrost_batch_adjust_stack_size(batch);
2999 panfrost_set_batch_masks_blend(batch);
3002 panfrost_set_batch_masks_zs(batch);
3007 batch->depth_stencil = panfrost_emit_depth_stencil(batch);
3010 batch->blend = panfrost_emit_blend_valhall(batch);
3013 batch->attribs[PIPE_SHADER_VERTEX] =
3014 panfrost_emit_vertex_data(batch);
3016 batch->attrib_bufs[PIPE_SHADER_VERTEX] =
3017 panfrost_emit_vertex_buffers(batch);
3024 panfrost_batch_get_bifrost_tiler(struct panfrost_batch *batch, unsigned vertex_count)
3026 struct panfrost_device *dev = pan_device(batch->ctx->base.screen);
3031 if (batch->tiler_ctx.bifrost)
3032 return batch->tiler_ctx.bifrost;
3035 pan_pool_alloc_desc(&batch->pool.base, TILER_HEAP);
3041 t = pan_pool_alloc_desc(&batch->pool.base, TILER_CONTEXT);
3042 GENX(pan_emit_tiler_ctx)(dev, batch->key.width, batch->key.height,
3043 util_framebuffer_get_num_samples(&batch->key),
3044 pan_tristate_get(batch->first_provoking_vertex),
3047 batch->tiler_ctx.bifrost = t.gpu;
3048 return batch->tiler_ctx.bifrost;
3134 panfrost_emit_resources(struct panfrost_batch *batch,
3138 struct panfrost_context *ctx = batch->ctx;
3145 T = pan_pool_alloc_aligned(&batch->pool.base, nr_tables * pan_size(RESOURCE), 64);
3151 batch->textures[stage],
3155 batch->samplers[stage],
3159 batch->images[stage],
3164 batch->attribs[stage],
3168 batch->attrib_bufs[stage],
3176 panfrost_emit_shader(struct panfrost_batch *batch,
3185 ubos = panfrost_emit_const_buf(batch, stage, &ubo_count, &cfg->fau,
3188 resources = panfrost_emit_resources(batch, stage, ubos, ubo_count);
3201 struct panfrost_batch *batch,
3206 struct panfrost_context *ctx = batch->ctx;
3231 panfrost_batch_write_rsrc(ctx->batch, rsrc,
3255 cfg.minimum_z = batch->minimum_z;
3256 cfg.maximum_z = batch->maximum_z;
3258 cfg.depth_stencil = batch->depth_stencil;
3304 cfg.blend = batch->blend;
3305 cfg.blend_count = MAX2(batch->key.nr_cbufs, 1);
3311 panfrost_emit_shader(batch, &cfg.shader, PIPE_SHADER_FRAGMENT,
3312 batch->rsd[PIPE_SHADER_FRAGMENT],
3313 batch->tls.gpu);
3337 cfg.state = batch->rsd[PIPE_SHADER_FRAGMENT];
3338 cfg.attributes = batch->attribs[PIPE_SHADER_FRAGMENT];
3339 cfg.attribute_buffers = batch->attrib_bufs[PIPE_SHADER_FRAGMENT];
3340 cfg.viewport = batch->viewport;
3343 cfg.thread_storage = batch->tls.gpu;
3355 pan_emit_draw_descs(batch, &cfg, PIPE_SHADER_FRAGMENT);
3362 panfrost_emit_malloc_vertex(struct panfrost_batch *batch,
3368 struct panfrost_context *ctx = batch->ctx;
3411 cfg.address = panfrost_batch_get_bifrost_tiler(batch, ~0);
3414 STATIC_ASSERT(sizeof(batch->scissor) == pan_size(SCISSOR));
3416 &batch->scissor, pan_size(SCISSOR));
3426 batch, fs_required, u_reduced_prim(info->mode), 0, 0, 0);
3430 mali_ptr vs_ptr = batch->rsd[PIPE_SHADER_VERTEX];
3436 panfrost_emit_shader(batch, &cfg, PIPE_SHADER_VERTEX, vs_ptr,
3437 batch->tls.gpu);
3447 mali_ptr ptr = batch->rsd[PIPE_SHADER_VERTEX] +
3450 panfrost_emit_shader(batch, &cfg, PIPE_SHADER_VERTEX,
3451 ptr, batch->tls.gpu);
3458 panfrost_draw_emit_tiler(struct panfrost_batch *batch,
3466 struct panfrost_context *ctx = batch->ctx;
3479 cfg.address = panfrost_batch_get_bifrost_tiler(batch, ~0);
3486 batch, true, prim, pos, fs_vary, varyings);
3493 panfrost_launch_xfb(struct panfrost_batch *batch,
3498 struct panfrost_context *ctx = batch->ctx;
3501 pan_pool_alloc_desc(&batch->pool.base, COMPUTE_JOB);
3504 if (batch->ctx->streamout.num_targets == 0)
3520 mali_ptr saved_rsd = batch->rsd[PIPE_SHADER_VERTEX];
3521 mali_ptr saved_ubo = batch->uniform_buffers[PIPE_SHADER_VERTEX];
3522 mali_ptr saved_push = batch->push_uniforms[PIPE_SHADER_VERTEX];
3525 batch->rsd[PIPE_SHADER_VERTEX] = panfrost_emit_compute_shader_meta(batch, PIPE_SHADER_VERTEX);
3537 panfrost_emit_shader(batch, &cfg.compute, PIPE_SHADER_VERTEX,
3538 batch->rsd[PIPE_SHADER_VERTEX],
3539 batch->tls.gpu);
3542 cfg.compute.attribute_offset = batch->ctx->offset_start;
3558 batch->uniform_buffers[PIPE_SHADER_VERTEX] =
3559 panfrost_emit_const_buf(batch, PIPE_SHADER_VERTEX, NULL,
3560 &batch->push_uniforms[PIPE_SHADER_VERTEX], NULL);
3562 panfrost_draw_emit_vertex(batch, info, &invocation, 0, 0,
3569 panfrost_add_job(&batch->pool.base, &batch->scoreboard, job_type,
3573 batch->rsd[PIPE_SHADER_VERTEX] = saved_rsd;
3574 batch->uniform_buffers[PIPE_SHADER_VERTEX] = saved_ubo;
3575 batch->push_uniforms[PIPE_SHADER_VERTEX] = saved_push;
3579 panfrost_direct_draw(struct panfrost_batch *batch,
3587 struct panfrost_context *ctx = batch->ctx;
3620 tiler = pan_pool_alloc_desc(&batch->pool.base, MALLOC_VERTEX_JOB);
3622 tiler = pan_pool_alloc_desc(&batch->pool.base, INDEXED_VERTEX_JOB);
3627 vertex = pan_pool_alloc_desc(&batch->pool.base, COMPUTE_JOB);
3628 tiler = pan_pool_alloc_desc(&batch->pool.base, TILER_JOB);
3637 indices = panfrost_get_index_buffer(batch, info, draw);
3639 indices = panfrost_get_index_buffer_bounded(batch, info, draw,
3688 panfrost_emit_varying_descriptor(batch,
3696 attribs = panfrost_emit_vertex_data(batch, &attrib_bufs);
3699 panfrost_update_state_3d(batch);
3700 panfrost_update_shader_state(batch, PIPE_SHADER_VERTEX);
3701 panfrost_update_shader_state(batch, PIPE_SHADER_FRAGMENT);
3708 panfrost_launch_xfb(batch, info, attribs, attrib_bufs, draw->count);
3717 if (panfrost_batch_skip_rasterization(batch))
3723 panfrost_emit_malloc_vertex(batch, info, draw, indices,
3726 panfrost_add_job(&batch->pool.base, &batch->scoreboard,
3731 panfrost_draw_emit_tiler(batch, info, draw, &invocation, indices,
3736 panfrost_draw_emit_vertex_section(batch,
3741 panfrost_add_job(&batch->pool.base, &batch->scoreboard,
3746 panfrost_draw_emit_vertex(batch, info, &invocation,
3748 panfrost_emit_vertex_tiler_jobs(batch, &vertex, &tiler);
3755 panfrost_indirect_draw(struct panfrost_batch *batch,
3764 struct panfrost_context *ctx = batch->ctx;
3784 tiler = pan_pool_alloc_desc(&batch->pool.base, INDEXED_VERTEX_JOB);
3789 vertex = pan_pool_alloc_desc(&batch->pool.base, COMPUTE_JOB);
3790 tiler = pan_pool_alloc_desc(&batch->pool.base, TILER_JOB);
3799 panfrost_batch_read_rsrc(batch, rsrc, PIPE_SHADER_VERTEX);
3818 panfrost_update_state_3d(batch);
3819 panfrost_update_shader_state(batch, PIPE_SHADER_VERTEX);
3820 panfrost_update_shader_state(batch, PIPE_SHADER_FRAGMENT);
3825 panfrost_emit_varying_descriptor(batch, 0,
3831 attribs = panfrost_emit_vertex_data(batch, &attrib_bufs);
3837 panfrost_draw_emit_tiler(batch, info, draw, &invocation,
3843 panfrost_draw_emit_vertex_section(batch,
3849 panfrost_draw_emit_vertex(batch, info, &invocation,
3853 /* Add the varying heap BO to the batch if we're allocating varyings. */
3855 panfrost_batch_add_bo(batch,
3869 panfrost_batch_read_rsrc(batch, draw_buf, PIPE_SHADER_VERTEX);
3872 .last_indirect_draw = batch->indirect_draw_job_id,
3901 batch->indirect_draw_job_id =
3902 GENX(panfrost_emit_indirect_draw)(&batch->pool.base,
3903 &batch->scoreboard,
3905 &batch->indirect_draw_ctx);
3908 panfrost_add_job(&batch->pool.base, &batch->scoreboard,
3912 panfrost_emit_vertex_tiler_jobs(batch, &vertex, &tiler);
3918 panfrost_compatible_batch_state(struct panfrost_batch *batch,
3925 struct panfrost_context *ctx = batch->ctx;
3935 return pan_tristate_set(&batch->sprite_coord_origin, coord);
3937 return pan_tristate_set(&batch->first_provoking_vertex, first);
3962 struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
3964 /* Don't add too many jobs to a single batch. Hardware has a hard limit
3967 if (unlikely(batch->scoreboard.job_index > 10000))
3968 batch = panfrost_get_fresh_batch_for_fbo(ctx, "Too many draws");
3972 if (unlikely(!panfrost_compatible_batch_state(batch, points))) {
3973 batch = panfrost_get_fresh_batch_for_fbo(ctx, "State change");
3975 ASSERTED bool succ = panfrost_compatible_batch_state(batch, points);
3976 assert(succ && "must be able to set state for a fresh batch");
3980 * batch->scissor_culls_everything, which is set by
3984 batch->viewport = panfrost_emit_viewport(batch);
4006 panfrost_direct_draw(batch, info, drawid_offset, &tmp_draw);
4010 panfrost_indirect_draw(batch, info, drawid_offset, indirect, &draws[0]);
4019 panfrost_direct_draw(batch, &tmp_info, drawid, &draws[i]);
4043 struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx);
4074 pan_pool_alloc_desc(&batch->pool.base, COMPUTE_JOB);
4096 panfrost_update_shader_state(batch, PIPE_SHADER_COMPUTE);
4113 cfg.state = batch->rsd[PIPE_SHADER_COMPUTE];
4114 cfg.attributes = panfrost_emit_image_attribs(batch, &cfg.attribute_buffers, PIPE_SHADER_COMPUTE);
4115 cfg.thread_storage = panfrost_emit_shared_memory(batch, info);
4116 cfg.uniform_buffers = batch->uniform_buffers[PIPE_SHADER_COMPUTE];
4117 cfg.push_uniforms = batch->push_uniforms[PIPE_SHADER_COMPUTE];
4118 cfg.textures = batch->textures[PIPE_SHADER_COMPUTE];
4119 cfg.samplers = batch->samplers[PIPE_SHADER_COMPUTE];
4131 panfrost_emit_shader(batch, &cfg.compute, PIPE_SHADER_COMPUTE,
4132 batch->rsd[PIPE_SHADER_COMPUTE],
4133 panfrost_emit_shared_memory(batch, info));
4149 batch->num_wg_sysval[0],
4150 batch->num_wg_sysval[1],
4151 batch->num_wg_sysval[2],
4155 indirect_dep = GENX(pan_indirect_dispatch_emit)(&batch->pool.base,
4156 &batch->scoreboard,
4161 panfrost_add_job(&batch->pool.base, &batch->scoreboard,
4627 preload(struct panfrost_batch *batch, struct pan_fb_info *fb)
4629 GENX(pan_preload_fb)(&batch->pool.base, &batch->scoreboard, fb, batch->tls.gpu,
4630 PAN_ARCH >= 6 ? batch->tiler_ctx.bifrost : 0, NULL);
4634 init_batch(struct panfrost_batch *batch)
4637 batch->framebuffer =
4639 pan_pool_alloc_desc(&batch->pool.base, FRAMEBUFFER);
4641 pan_pool_alloc_desc_aggregate(&batch->pool.base,
4644 PAN_DESC_ARRAY(MAX2(batch->key.nr_cbufs, 1), RENDER_TARGET));
4646 batch->framebuffer.gpu |= MALI_FBD_TAG_IS_MFBD;
4650 batch->tls = pan_pool_alloc_desc(&batch->pool.base, LOCAL_STORAGE);
4653 batch->tls = batch->framebuffer;
4690 * since we'll hit the BO cache and this is one-per-batch anyway. */
4693 batch_get_polygon_list(struct panfrost_batch *batch)
4695 struct panfrost_device *dev = pan_device(batch->ctx->base.screen);
4697 if (!batch->tiler_ctx.midgard.polygon_list) {
4698 bool has_draws = batch->scoreboard.first_tiler != NULL;
4701 batch->key.width,
4702 batch->key.height,
4710 batch->tiler_ctx.midgard.polygon_list =
4711 panfrost_batch_create_bo(batch, size,
4715 panfrost_batch_add_bo(batch, batch->tiler_ctx.midgard.polygon_list,
4719 assert(batch->tiler_ctx.midgard.polygon_list->ptr.cpu);
4721 batch->tiler_ctx.midgard.polygon_list->ptr.cpu +
4728 batch->tiler_ctx.midgard.disable = !has_draws;
4731 return batch->tiler_ctx.midgard.polygon_list->ptr.gpu;
4736 init_polygon_list(struct panfrost_batch *batch)
4739 mali_ptr polygon_list = batch_get_polygon_list(batch);
4740 panfrost_scoreboard_initialize_tiler(&batch->pool.base,
4741 &batch->scoreboard,