Lines Matching defs:info
263 if (fs->info.fs.sidefx)
275 if (state->cbufs[i] && !blend->info[i].no_colour)
281 return (fs->info.fs.writes_depth || fs->info.fs.writes_stencil);
333 const struct pan_blend_info info = so->info[i];
335 bool enabled = ctx->pipe_framebuffer.cbufs[i] && info.no_colour;
336 bool flag = zero ? info.alpha_zero_nop : info.alpha_one_store;
358 if (rt_count == 0 || !batch->key.cbufs[i] || so->info[i].no_colour) {
369 struct pan_blend_info info = so->info[i];
371 float cons = pan_blend_get_constant(info.constant_mask,
377 cfg.load_destination = info.load_dest;
419 unsigned ret_offset = fs->info.bifrost.blend[i].return_offset;
428 cfg.mode = info.opaque ?
439 fs->info.bifrost.blend[i].format;
443 if (!info.opaque) {
444 cfg.fixed_function.alpha_zero_nop = info.alpha_zero_nop;
445 cfg.fixed_function.alpha_one_store = info.alpha_one_store;
462 uint64_t rt_written = (fs->info.outputs_written >> FRAG_RESULT_DATA0);
466 return fs->info.fs.can_fpk &&
551 fs->info.fs.can_early_z && !alpha_to_coverage &&
556 cfg.properties.work_register_count = MAX2(fs->info.work_reg_count, 8);
558 cfg.properties.work_register_count = fs->info.work_reg_count;
565 force_ez_with_discard && fs->info.fs.can_discard;
567 !force_ez_with_discard && fs->info.fs.can_discard;
573 cfg.multisample_misc.load_destination = so->info[0].load_dest;
575 cfg.stencil_mask_misc.write_enable = !so->info[0].no_colour;
584 so->info[0].constant_mask,
823 cfg.stencil_from_shader = fs->info.fs.writes_stencil;
824 cfg.depth_source = pan_depth_source(&fs->info);
1289 for (unsigned i = 0; i < ss->info.sysvals.sysval_count; ++i) {
1290 int sysval = ss->info.sysvals.sysvals[i];
1473 size_t sys_size = sizeof(float) * 4 * ss->info.sysvals.sysval_count;
1482 unsigned ubo_count = shader->info.ubo_count - (sys_size ? 1 : 0);
1506 u_foreach_bit(ubo, ss->info.ubo_mask & buf->enabled_mask) {
1519 *pushed_words = ss->info.push.count;
1521 if (ss->info.push.count == 0)
1527 ss->info.push.count * 4, 16);
1532 for (unsigned i = 0; i < ss->info.push.count; ++i) {
1533 struct panfrost_ubo_word src = ss->info.push.words[i];
1538 unsigned sysval_type = PAN_SYSVAL_TYPE(ss->info.sysvals.sysvals[sysval_idx]);
1595 struct pan_tls_info info = {
1596 .tls.size = ss->info.tls_size,
1597 .wls.size = ss->info.wls_size,
1603 if (ss->info.tls_size) {
1606 ss->info.tls_size,
1609 info.tls.ptr = bo->ptr.gpu;
1612 if (ss->info.wls_size) {
1614 pan_wls_adjust_size(info.wls.size) *
1615 pan_wls_instances(&info.wls.dim) *
1621 info.wls.ptr = bo->ptr.gpu;
1624 GENX(pan_emit_tls)(&info, t.cpu);
1957 if (!shader->info.attribute_count) {
1963 unsigned attr_count = shader->info.attribute_count;
2004 unsigned count = vs->info.attribute_count;
2007 count = MAX2(count, vs->xfb->info.attribute_count);
2197 assert(vs->info.attributes_read_count <= so->num_elements);
2199 for (unsigned i = 0; i < vs->info.attributes_read_count; ++i) {
2270 /* Enable special buffers by the shader info */
2451 unsigned producer_count = producer->info.varyings.output_count;
2452 unsigned consumer_count = consumer->info.varyings.input_count;
2478 out->present = pan_varying_present(dev, &producer->info,
2479 &consumer->info, point_coord_mask);
2481 out->stride = pan_assign_varyings(dev, &producer->info,
2482 &consumer->info, offsets);
2485 signed j = pan_find_vary(consumer->info.varyings.input,
2486 consumer->info.varyings.input_count,
2487 producer->info.varyings.output[i].location);
2490 consumer->info.varyings.input[j].format :
2491 producer->info.varyings.output[i].format;
2494 producer->info.varyings.output[i], format,
2499 signed j = pan_find_vary(producer->info.varyings.output,
2500 producer->info.varyings.output_count,
2501 consumer->info.varyings.input[i].location);
2506 consumer->info.varyings.input[i],
2507 consumer->info.varyings.input[i].format,
2560 !vs->info.separable &&
2561 !fs->info.separable;
2795 const struct pipe_draw_info *info,
2801 uint32_t prims = u_prims_for_vertices(info->mode, draw->count);
2869 const struct pipe_draw_info *info,
2908 panfrost_is_implicit_prim_restart(const struct pipe_draw_info *info)
2912 return info->primitive_restart &&
2913 info->restart_index == (unsigned)BITFIELD_MASK(info->index_size * 8);
3057 const struct pipe_draw_info *info,
3063 bool lines = (info->mode == PIPE_PRIM_LINES ||
3064 info->mode == PIPE_PRIM_LINE_LOOP ||
3065 info->mode == PIPE_PRIM_LINE_STRIP);
3068 cfg.draw_mode = pan_draw_mode(info->mode);
3082 if (panfrost_is_implicit_prim_restart(info)) {
3084 } else if (info->primitive_restart) {
3086 cfg.primitive_restart_index = info->restart_index;
3094 cfg.allow_rotating_primitives = !(lines || fs->info.bifrost.uses_flat_shading);
3095 cfg.primitive_restart = info->primitive_restart;
3098 assert(!cfg.primitive_restart || panfrost_is_implicit_prim_restart(info));
3102 cfg.index_type = panfrost_translate_index_size(info->index_size);
3273 cfg.allow_forward_pixel_to_be_killed = !fs->info.writes_global;
3285 (fs->info.outputs_written >> FRAG_RESULT_DATA0) &
3290 cfg.evaluate_per_sample |= fs->info.fs.sample_shading;
3295 cfg.shader_modifies_coverage = fs->info.fs.writes_coverage ||
3296 fs->info.fs.can_discard ||
3363 const struct pipe_draw_info *info,
3385 panfrost_emit_primitive(ctx, info, draw, 0, secondary_shader,
3389 cfg.count = info->instance_count;
3394 unsigned v = vs->info.varyings.output_count;
3395 unsigned f = fs->info.varyings.input_count;
3418 panfrost_emit_primitive_size(ctx, info->mode == PIPE_PRIM_POINTS, 0,
3426 batch, fs_required, u_reduced_prim(info->mode), 0, 0, 0);
3433 if (vs_ptr && info->mode != PIPE_PRIM_POINTS)
3459 const struct pipe_draw_info *info,
3471 panfrost_emit_primitive(ctx, info, draw, indices, secondary_shader,
3475 enum pipe_prim_type prim = u_reduced_prim(info->mode);
3494 const struct pipe_draw_info *info,
3508 //assert(info->index_size == 0);
3509 u_trim_pipe_prim(info->mode, &count);
3534 cfg.workgroup_count_y = info->instance_count;
3555 1, count, info->instance_count,
3562 panfrost_draw_emit_vertex(batch, info, &invocation, 0, 0,
3580 const struct pipe_draw_info *info,
3584 if (!draw->count || !info->instance_count)
3596 (info->mode == PIPE_PRIM_POINTS))) {
3598 ctx->active_prim = info->mode;
3604 ctx->vertex_count = draw->count + (info->index_size ? abs(draw->index_bias) : 0);
3605 ctx->instance_count = info->instance_count;
3606 ctx->base_vertex = info->index_size ? draw->index_bias : 0;
3607 ctx->base_instance = info->start_instance;
3608 ctx->active_prim = info->mode;
3613 bool idvs = vs->info.vs.idvs;
3614 bool secondary_shader = vs->info.vs.secondary_enable;
3636 if (info->index_size && PAN_ARCH >= 9) {
3637 indices = panfrost_get_index_buffer(batch, info, draw);
3638 } else if (info->index_size) {
3639 indices = panfrost_get_index_buffer_bounded(batch, info, draw,
3650 if (info->instance_count > 1) {
3665 panfrost_statistics_record(ctx, info, draw);
3669 if (info->instance_count > 1) {
3671 1, vertex_count, info->instance_count,
3693 info->mode == PIPE_PRIM_POINTS);
3708 panfrost_launch_xfb(batch, info, attribs, attrib_bufs, draw->count);
3723 panfrost_emit_malloc_vertex(batch, info, draw, indices,
3731 panfrost_draw_emit_tiler(batch, info, draw, &invocation, indices,
3746 panfrost_draw_emit_vertex(batch, info, &invocation,
3756 const struct pipe_draw_info *info,
3771 ctx->active_prim = info->mode;
3777 bool idvs = vs->info.vs.idvs;
3778 bool secondary_shader = vs->info.vs.secondary_enable;
3795 if (info->index_size) {
3796 assert(!info->has_user_indices);
3797 struct panfrost_resource *rsrc = pan_resource(info->index.resource);
3823 bool point_coord_replace = (info->mode == PIPE_PRIM_POINTS);
3837 panfrost_draw_emit_tiler(batch, info, draw, &invocation,
3849 panfrost_draw_emit_vertex(batch, info, &invocation,
3866 vs->info.attribute_count -
3884 .index_size = info->index_size,
3890 if (vs->info.vs.writes_point_size)
3896 if (info->primitive_restart) {
3897 draw_info.restart_index = info->restart_index;
3942 const struct pipe_draw_info *info,
3957 util_draw_indirect(pipe, info, indirect);
3970 bool points = (info->mode == PIPE_PRIM_POINTS);
4006 panfrost_direct_draw(batch, info, drawid_offset, &tmp_draw);
4010 panfrost_indirect_draw(batch, info, drawid_offset, indirect, &draws[0]);
4015 struct pipe_draw_info tmp_info = *info;
4035 const struct pipe_grid_info *info)
4050 if (info->indirect && ((cs->info.wls_size != 0) || !PAN_GPU_INDIRECTS)) {
4052 uint32_t *params = pipe_buffer_map_range(pipe, info->indirect,
4053 info->indirect_offset,
4058 struct pipe_grid_info direct = *info;
4071 ctx->compute_grid = info;
4083 .user_buffer = info->input
4086 if (info->input)
4089 /* Invoke according to the grid info */
4091 unsigned num_wg[3] = { info->grid[0], info->grid[1], info->grid[2] };
4093 if (info->indirect)
4101 info->block[0], info->block[1],
4102 info->block[2],
4103 false, info->indirect != NULL);
4107 util_logbase2_ceil(info->block[0] + 1) +
4108 util_logbase2_ceil(info->block[1] + 1) +
4109 util_logbase2_ceil(info->block[2] + 1);
4115 cfg.thread_storage = panfrost_emit_shared_memory(batch, info);
4123 cfg.workgroup_size_x = info->block[0];
4124 cfg.workgroup_size_y = info->block[1];
4125 cfg.workgroup_size_z = info->block[2];
4133 panfrost_emit_shared_memory(batch, info));
4135 cfg.allow_merging_workgroups = cs->info.cs.allow_merging_workgroups;
4143 if (info->indirect) {
4146 .indirect_dim = pan_resource(info->indirect)->image.data.bo->ptr.gpu +
4147 info->indirect_offset,
4486 so->info[c] = (struct pan_blend_info) {
4510 if (so->info[c].load_dest)
4515 if (so->info[c].fixed_function) {
4539 pan_shader_prepare_rsd(&state->info, state->bin.gpu, &cfg);
4553 bool vs = (state->info.stage == MESA_SHADER_VERTEX);
4554 bool secondary_enable = (vs && state->info.vs.secondary_enable);
4565 cfg.stage = pan_shader_stage(&state->info);
4567 cfg.register_allocation = pan_register_allocation(state->info.work_reg_count);
4569 cfg.preload.r48_r63 = (state->info.preload >> 48);
4572 cfg.requires_helper_threads = state->info.contains_barrier;
4580 cfg.stage = pan_shader_stage(&state->info);
4582 cfg.register_allocation = pan_register_allocation(state->info.work_reg_count);
4583 cfg.binary = state->bin.gpu + state->info.vs.no_psiz_offset;
4584 cfg.preload.r48_r63 = (state->info.preload >> 48);
4591 unsigned work_count = state->info.vs.secondary_work_reg_count;
4593 cfg.stage = pan_shader_stage(&state->info);
4596 cfg.binary = state->bin.gpu + state->info.vs.secondary_offset;
4597 cfg.preload.r48_r63 = (state->info.vs.secondary_preload >> 48);