Lines Matching refs:buffer
183 * buffer. Also updates buf->data if present.
240 /* Does a CPU wait for the buffer's backing data to become reliably accessible
241 * for write/read by waiting on the buffer's relevant fences.
317 /* Creates a cache in system memory of the buffer data. */
421 * buffer is busy due to GPU activity, because the contents were
438 /* The GPU is currently writing to this buffer. Copy its current
449 /* The buffer is currently idle. Create a staging area for writes,
476 * reasonable buffer for that case.
491 /* If the GPU is currently reading/writing this buffer, we shouldn't
514 /* It is expected that the returned buffer be a representation of the
515 * data in question, so we must copy it over from the buffer. */
549 * Also marks vbo dirty based on the buffer's binding
683 struct nv04_resource *buffer;
686 buffer = CALLOC_STRUCT(nv04_resource);
687 if (!buffer)
690 buffer->base = *templ;
691 pipe_reference_init(&buffer->base.reference, 1);
692 buffer->base.screen = pscreen;
694 if (buffer->base.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
696 buffer->domain = NOUVEAU_BO_GART;
697 } else if (buffer->base.bind == 0 || (buffer->base.bind &
699 switch (buffer->base.usage) {
702 buffer->domain = NV_VRAM_DOMAIN(screen);
708 buffer->domain = NV_VRAM_DOMAIN(screen);
712 buffer->domain = NOUVEAU_BO_GART;
719 if (buffer->base.bind & screen->vidmem_bindings)
720 buffer->domain = NV_VRAM_DOMAIN(screen);
722 if (buffer->base.bind & screen->sysmem_bindings)
723 buffer->domain = NOUVEAU_BO_GART;
726 ret = nouveau_buffer_allocate(screen, buffer, buffer->domain);
731 if (buffer->domain == NOUVEAU_BO_VRAM && screen->hint_buf_keep_sysmem_copy)
732 nouveau_buffer_cache(NULL, buffer);
736 util_range_init(&buffer->valid_buffer_range);
738 return &buffer->base;
741 FREE(buffer);
750 struct nv04_resource *buffer;
752 buffer = CALLOC_STRUCT(nv04_resource);
753 if (!buffer)
756 buffer->base = *templ;
761 buffer->address = (uintptr_t)user_ptr;
762 buffer->data = user_ptr;
763 buffer->status = NOUVEAU_BUFFER_STATUS_USER_PTR;
764 buffer->base.screen = pscreen;
766 pipe_reference_init(&buffer->base.reference, 1);
768 return &buffer->base;
775 struct nv04_resource *buffer;
777 buffer = CALLOC_STRUCT(nv04_resource);
778 if (!buffer)
781 pipe_reference_init(&buffer->base.reference, 1);
782 buffer->base.screen = pscreen;
783 buffer->base.format = PIPE_FORMAT_R8_UNORM;
784 buffer->base.usage = PIPE_USAGE_IMMUTABLE;
785 buffer->base.bind = bind;
786 buffer->base.width0 = bytes;
787 buffer->base.height0 = 1;
788 buffer->base.depth0 = 1;
790 buffer->data = ptr;
791 buffer->status = NOUVEAU_BUFFER_STATUS_USER_MEMORY;
793 util_range_init(&buffer->valid_buffer_range);
794 util_range_add(&buffer->base, &buffer->valid_buffer_range, 0, bytes);
796 return &buffer->base;
811 /* Migrate a linear buffer (vertex, index, constants) USER -> GART -> VRAM. */
908 /* Invalidate underlying buffer storage, reset fences, reallocate to non-busy
909 * buffer.
925 /* If the buffer is sub-allocated and not currently being written, just
926 * wipe the valid buffer range. Otherwise we have to create fresh
1009 /* Continue to next scratch buffer, if available (no wrapping, large enough).
1052 /* Copy data to a scratch buffer and return address & bo the data resides in. */