Lines Matching refs:ds
30 #include "ds/intel_driver_ds.h"
70 container_of(utctx, struct iris_context, ds.trace_context);
98 intel_ds_flush_data_init(flush_data, batch->ds, submission_id);
117 intel_ds_device_init(&ice->ds, &screen->devinfo, screen->fd, minor % 128,
119 u_trace_pipe_context_init(&ice->ds.trace_context, &ice->ctx,
125 ice->batches[i].ds =
126 intel_ds_device_add_queue(&ice->ds, "%s",
133 intel_ds_device_fini(&ice->ds);
141 enum intel_ds_stall_flag ds;
143 { .iris = PIPE_CONTROL_DEPTH_CACHE_FLUSH, .ds = INTEL_DS_DEPTH_CACHE_FLUSH_BIT, },
144 { .iris = PIPE_CONTROL_DATA_CACHE_FLUSH, .ds = INTEL_DS_DATA_CACHE_FLUSH_BIT, },
145 { .iris = PIPE_CONTROL_TILE_CACHE_FLUSH, .ds = INTEL_DS_TILE_CACHE_FLUSH_BIT, },
146 { .iris = PIPE_CONTROL_RENDER_TARGET_FLUSH, .ds = INTEL_DS_RENDER_TARGET_CACHE_FLUSH_BIT, },
147 { .iris = PIPE_CONTROL_STATE_CACHE_INVALIDATE, .ds = INTEL_DS_STATE_CACHE_INVALIDATE_BIT, },
148 { .iris = PIPE_CONTROL_CONST_CACHE_INVALIDATE, .ds = INTEL_DS_CONST_CACHE_INVALIDATE_BIT, },
149 { .iris = PIPE_CONTROL_VF_CACHE_INVALIDATE, .ds = INTEL_DS_VF_CACHE_INVALIDATE_BIT, },
150 { .iris = PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE, .ds = INTEL_DS_TEXTURE_CACHE_INVALIDATE_BIT, },
151 { .iris = PIPE_CONTROL_INSTRUCTION_INVALIDATE, .ds = INTEL_DS_INST_CACHE_INVALIDATE_BIT, },
152 { .iris = PIPE_CONTROL_DEPTH_STALL, .ds = INTEL_DS_DEPTH_STALL_BIT, },
153 { .iris = PIPE_CONTROL_CS_STALL, .ds = INTEL_DS_CS_STALL_BIT, },
154 { .iris = PIPE_CONTROL_FLUSH_HDC, .ds = INTEL_DS_HDC_PIPELINE_FLUSH_BIT, },
155 { .iris = PIPE_CONTROL_STALL_AT_SCOREBOARD, .ds = INTEL_DS_STALL_AT_SCOREBOARD_BIT, },
161 ret |= iris_to_ds_flags[i].ds;