Lines Matching refs:res
409 iris_get_depth_stencil_resources(struct pipe_resource *res,
413 if (!res) {
419 if (res->format != PIPE_FORMAT_S8_UINT) {
420 *out_z = (void *) res;
421 *out_s = (void *) iris_resource_get_separate_stencil(res);
424 *out_s = (void *) res;
429 iris_resource_disable_aux(struct iris_resource *res)
431 iris_bo_unreference(res->aux.bo);
432 iris_bo_unreference(res->aux.clear_color_bo);
433 free(res->aux.state);
435 res->aux.usage = ISL_AUX_USAGE_NONE;
436 res->aux.surf.size_B = 0;
437 res->aux.bo = NULL;
438 res->aux.extra_aux.surf.size_B = 0;
439 res->aux.clear_color_bo = NULL;
440 res->aux.state = NULL;
490 struct iris_resource *res = (struct iris_resource *) p_res;
493 util_range_destroy(&res->valid_buffer_range);
495 iris_resource_disable_aux(res);
498 iris_bo_unreference(res->bo);
499 iris_pscreen_unref(res->orig_screen);
501 free(res);
508 struct iris_resource *res = calloc(1, sizeof(struct iris_resource));
509 if (!res)
512 res->base.b = *templ;
513 res->base.b.screen = pscreen;
514 res->orig_screen = iris_pscreen_ref(pscreen);
515 pipe_reference_init(&res->base.b.reference, 1);
516 threaded_resource_init(&res->base.b, false);
519 util_range_init(&res->valid_buffer_range);
521 return res;
525 iris_get_num_logical_layers(const struct iris_resource *res, unsigned level)
527 if (res->surf.dim == ISL_SURF_DIM_3D)
528 return u_minify(res->surf.logical_level0_px.depth, level);
530 return res->surf.logical_level0_px.array_len;
534 create_aux_state_map(struct iris_resource *res, enum isl_aux_state initial)
536 assert(res->aux.state == NULL);
539 for (uint32_t level = 0; level < res->surf.levels; level++)
540 total_slices += iris_get_num_logical_layers(res, level);
543 res->surf.levels * sizeof(enum isl_aux_state *);
558 for (uint32_t level = 0; level < res->surf.levels; level++) {
560 const unsigned level_layers = iris_get_num_logical_layers(res, level);
571 struct iris_resource *res)
573 if (!isl_aux_usage_has_fast_clears(res->aux.usage))
576 assert(!isl_surf_usage_is_stencil(res->surf.usage));
582 if (isl_surf_usage_is_depth(res->surf.usage) &&
583 !iris_sample_with_depth_aux(&screen->devinfo, res))
590 map_aux_addresses(struct iris_screen *screen, struct iris_resource *res,
597 if (isl_aux_usage_has_ccs(res->aux.usage)) {
598 const unsigned aux_offset = res->aux.extra_aux.surf.size_B > 0 ?
599 res->aux.extra_aux.offset : res->aux.offset;
601 iris_format_for_usage(&screen->devinfo, pfmt, res->surf.usage).fmt;
603 intel_aux_map_format_bits(res->surf.tiling, format, plane);
604 intel_aux_map_add_mapping(aux_map_ctx, res->bo->address + res->offset,
605 res->aux.bo->address + aux_offset,
606 res->surf.size_B, format_bits);
607 res->bo->aux_map_address = res->aux.bo->address;
658 struct iris_resource *res,
662 res->mod_info = isl_drm_modifier_get_info(modifier);
664 if (modifier != DRM_FORMAT_MOD_INVALID && res->mod_info == NULL)
669 if (res->mod_info != NULL) {
670 tiling_flags = 1 << res->mod_info->tiling;
685 if (res->mod_info && res->mod_info->aux_usage == ISL_AUX_USAGE_NONE)
736 if (!isl_surf_init_s(&screen->isl_dev, &res->surf, &init_info))
739 res->internal_format = templ->format;
785 struct iris_resource *res, bool imported)
790 isl_surf_get_mcs_surf(&screen->isl_dev, &res->surf, &res->aux.surf);
793 isl_surf_get_hiz_surf(&screen->isl_dev, &res->surf, &res->aux.surf);
796 iris_get_ccs_surf_or_support(&screen->isl_dev, &res->surf,
797 &res->aux.surf, &res->aux.extra_aux.surf);
800 assert(!res->mod_info);
803 res->aux.usage = ISL_AUX_USAGE_MCS_CCS;
805 res->aux.usage = ISL_AUX_USAGE_MCS;
808 assert(!res->mod_info);
811 res->aux.usage = ISL_AUX_USAGE_HIZ;
812 } else if (res->surf.samples == 1 &&
813 (res->surf.usage & ISL_SURF_USAGE_TEXTURE_BIT)) {
818 res->aux.usage = ISL_AUX_USAGE_HIZ_CCS_WT;
820 res->aux.usage = ISL_AUX_USAGE_HIZ_CCS;
823 if (res->mod_info) {
824 res->aux.usage = res->mod_info->aux_usage;
825 } else if (isl_surf_usage_is_stencil(res->surf.usage)) {
826 res->aux.usage = ISL_AUX_USAGE_STC_CCS;
827 } else if (want_ccs_e_for_format(devinfo, res->surf.format)) {
828 res->aux.usage = devinfo->ver < 12 ?
831 assert(isl_format_supports_ccs_d(devinfo, res->surf.format));
832 res->aux.usage = ISL_AUX_USAGE_CCS_D;
837 switch (res->aux.usage) {
840 return !res->mod_info || res->mod_info->aux_usage == ISL_AUX_USAGE_NONE;
865 assert(res->aux.usage != ISL_AUX_USAGE_STC_CCS);
867 isl_drm_modifier_get_default_aux_state(res->mod_info->modifier);
869 assert(res->aux.surf.size_B == 0);
879 assert(isl_aux_usage_has_compression(res->aux.usage));
880 initial_state = isl_aux_usage_has_fast_clears(res->aux.usage) ?
884 assert(res->aux.surf.size_B > 0);
903 res->aux.state = create_aux_state_map(res, initial_state);
904 if (!res->aux.state)
917 struct iris_resource *res)
921 if (iris_resource_get_aux_state(res, 0, 0) != ISL_AUX_STATE_AUX_INVALID &&
922 res->aux.surf.size_B > 0) {
924 map = iris_bo_map(NULL, res->bo, MAP_WRITE | MAP_RAW);
929 uint8_t memset_value = isl_aux_usage_has_mcs(res->aux.usage) ? 0xFF : 0;
930 memset((char*)map + res->aux.offset, memset_value,
931 res->aux.surf.size_B);
934 if (res->aux.extra_aux.surf.size_B > 0) {
936 map = iris_bo_map(NULL, res->bo, MAP_WRITE | MAP_RAW);
940 memset((char*)map + res->aux.extra_aux.offset,
941 0, res->aux.extra_aux.surf.size_B);
944 unsigned clear_color_size = iris_get_aux_clear_color_state_size(screen, res);
946 if (iris_bo_mmap_mode(res->bo) != IRIS_MMAP_NONE) {
948 map = iris_bo_map(NULL, res->bo, MAP_WRITE | MAP_RAW);
953 memset((char *)map + res->aux.clear_color_offset, 0, clear_color_size);
955 res->aux.clear_color_unknown = true;
960 iris_bo_unmap(res->bo);
962 if (res->aux.surf.size_B > 0) {
963 res->aux.bo = res->bo;
964 iris_bo_reference(res->aux.bo);
965 map_aux_addresses(screen, res, res->internal_format, 0);
969 res->aux.clear_color_bo = res->bo;
970 iris_bo_reference(res->aux.clear_color_bo);
977 import_aux_info(struct iris_resource *res,
981 assert(res->bo == aux_res->aux.bo);
982 assert(res->aux.surf.row_pitch_B == aux_res->aux.surf.row_pitch_B);
983 assert(res->bo->size >= aux_res->aux.offset + res->aux.surf.size_B);
986 res->aux.bo = aux_res->aux.bo;
987 res->aux.offset = aux_res->aux.offset;
992 struct iris_resource *res)
1002 for (struct pipe_resource *p_res = &res->base.b; p_res; p_res = p_res->next) {
1008 switch (res->mod_info->modifier) {
1013 map_aux_addresses(screen, r[0], res->external_format, 0);
1021 if (iris_get_aux_clear_color_state_size(screen, res) > 0) {
1022 res->aux.clear_color_bo =
1024 iris_get_aux_clear_color_state_size(screen, res),
1031 res->aux.clear_color_bo =
1033 iris_get_aux_clear_color_state_size(screen, res),
1039 map_aux_addresses(screen, r[0], res->external_format, 0);
1060 map_aux_addresses(screen, r[0], res->external_format, 0);
1065 map_aux_addresses(screen, r[0], res->external_format, 0);
1066 map_aux_addresses(screen, r[1], res->external_format, 1);
1068 assert(!isl_aux_usage_has_fast_clears(res->mod_info->aux_usage));
1071 assert(!isl_aux_usage_has_fast_clears(res->mod_info->aux_usage));
1074 assert(res->mod_info->aux_usage == ISL_AUX_USAGE_NONE);
1100 struct iris_resource *res = iris_alloc_resource(pscreen, templ);
1108 res->internal_format = templ->format;
1109 res->surf.tiling = ISL_TILING_LINEAR;
1127 unsigned flags = iris_resource_alloc_flags(screen, templ, res->aux.usage);
1129 res->bo = iris_bo_alloc(screen->bufmgr, name, templ->width0,
1133 if (!res->bo) {
1134 iris_resource_destroy(pscreen, &res->base.b);
1139 iris_bo_mark_exported(res->bo);
1140 res->base.is_shared = true;
1143 return &res->base.b;
1154 struct iris_resource *res = iris_alloc_resource(pscreen, templ);
1156 if (!res)
1168 iris_resource_configure_main(screen, res, templ, modifier, 0);
1171 if (!iris_resource_configure_aux(screen, res, false))
1177 unsigned flags = iris_resource_alloc_flags(screen, templ, res->aux.usage);
1188 uint64_t bo_size = res->surf.size_B;
1191 if (res->aux.surf.size_B > 0) {
1192 res->aux.offset = ALIGN(bo_size, res->aux.surf.alignment_B);
1193 bo_size = res->aux.offset + res->aux.surf.size_B;
1197 if (res->aux.extra_aux.surf.size_B > 0) {
1198 res->aux.extra_aux.offset =
1199 ALIGN(bo_size, res->aux.extra_aux.surf.alignment_B);
1200 bo_size = res->aux.extra_aux.offset + res->aux.extra_aux.surf.size_B;
1209 if (iris_get_aux_clear_color_state_size(screen, res) > 0) {
1210 res->aux.clear_color_offset = ALIGN(bo_size, 4096);
1211 bo_size = res->aux.clear_color_offset +
1212 iris_get_aux_clear_color_state_size(screen, res);
1215 uint32_t alignment = MAX2(4096, res->surf.alignment_B);
1216 res->bo =
1219 if (!res->bo)
1222 if (res->aux.usage != ISL_AUX_USAGE_NONE &&
1223 !iris_resource_init_aux_buf(screen, res))
1227 iris_bo_mark_exported(res->bo);
1228 res->base.is_shared = true;
1231 return &res->base.b;
1235 iris_resource_destroy(pscreen, &res->base.b);
1270 struct iris_resource *res = iris_alloc_resource(pscreen, templ);
1271 if (!res)
1288 if (!iris_resource_configure_main(screen, res, templ,
1291 iris_resource_destroy(pscreen, &res->base.b);
1294 assert(res->surf.size_B <= res_size);
1310 res->internal_format = templ->format;
1311 res->base.is_user_ptr = true;
1312 res->bo = iris_bo_create_userptr(bufmgr, "user", mem_start, mem_size,
1314 res->offset = offset;
1315 if (!res->bo) {
1316 iris_resource_destroy(pscreen, &res->base.b);
1320 util_range_add(&res->base.b, &res->valid_buffer_range, 0, templ->width0);
1322 return &res->base.b;
1365 struct iris_resource *res = iris_alloc_resource(pscreen, templ);
1366 if (!res)
1371 res->bo = iris_bo_import_dmabuf(bufmgr, whandle->handle);
1374 res->bo = iris_bo_gem_create_from_name(bufmgr, "winsys image",
1380 if (!res->bo)
1383 res->offset = whandle->offset;
1384 res->external_format = whandle->format;
1393 iris_gem_get_tiling(res->bo, &tiling);
1398 iris_resource_configure_main(screen, res, templ, modifier,
1402 UNUSED const bool ok = iris_resource_configure_aux(screen, res, true);
1409 res->aux.clear_color_offset = whandle->offset;
1410 res->aux.clear_color_bo = res->bo;
1411 res->bo = NULL;
1415 * image with res->base.next. See iris_resource_finish_aux_import.
1417 res->aux.surf.row_pitch_B = whandle->stride;
1418 res->aux.offset = whandle->offset;
1419 res->aux.bo = res->bo;
1420 res->bo = NULL;
1423 if (get_num_planes(&res->base.b) ==
1426 iris_resource_finish_aux_import(pscreen, res);
1429 return &res->base.b;
1432 iris_resource_destroy(pscreen, &res->base.b);
1444 struct iris_resource *res = iris_alloc_resource(pscreen, templ);
1446 if (!res)
1451 iris_resource_configure_main(screen, res, templ, DRM_FORMAT_MOD_INVALID, 0);
1455 res->bo = memobj->bo;
1456 res->offset = offset;
1457 res->external_format = memobj->format;
1458 res->internal_format = templ->format;
1462 return &res->base.b;
1489 struct iris_resource *res = (struct iris_resource *) prsc;
1493 ALIGN(res->surf.size_B, res->surf.alignment_B);
1513 struct iris_resource *res = (void *) resource;
1514 const struct isl_drm_modifier_info *mod = res->mod_info;
1516 iris_resource_prepare_access(ice, res,
1522 if (!res->mod_info && res->aux.usage != ISL_AUX_USAGE_NONE) {
1529 if (iris_batch_references(batch, res->bo))
1533 iris_resource_disable_aux(res);
1634 struct iris_resource *res)
1636 if (iris_bo_is_real(res->bo))
1639 assert(!(res->base.b.bind & PIPE_BIND_SHARED));
1660 iris_reallocate_resource_inplace(ice, res, PIPE_BIND_SHARED);
1661 assert(res->base.b.bind & PIPE_BIND_SHARED);
1672 struct iris_resource *res = (struct iris_resource *)resource;
1674 res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;
1681 (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) && res->aux.usage != 0) &&
1683 iris_resource_disable_aux(res);
1699 struct iris_resource *res = (struct iris_resource *)resource;
1701 res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;
1704 mod_plane_is_clear_color(res->mod_info->modifier, plane);
1709 iris_resource_disable_suballoc_on_first_query(pscreen, ctx, res);
1711 struct iris_bo *bo = wants_cc ? res->aux.clear_color_bo :
1712 wants_aux ? res->aux.bo : res->bo;
1720 res->mod_info->modifier,
1721 res->external_format);
1723 *value = get_num_planes(&res->base.b);
1728 wants_aux ? res->aux.surf.row_pitch_B : res->surf.row_pitch_B;
1742 *value = wants_cc ? res->aux.clear_color_offset :
1743 wants_aux ? res->aux.offset : 0;
1746 *value = res->mod_info ? res->mod_info->modifier :
1747 tiling_to_modifier(isl_tiling_to_i915_tiling(res->surf.tiling));
1751 iris_gem_set_tiling(bo, &res->surf);
1759 iris_gem_set_tiling(bo, &res->surf);
1775 iris_gem_set_tiling(bo, &res->surf);
1794 struct iris_resource *res = (struct iris_resource *)resource;
1796 res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;
1799 iris_resource_disable_suballoc_on_first_query(pscreen, ctx, res);
1801 assert(iris_bo_is_real(res->bo));
1804 if (res->mod_info &&
1805 mod_plane_is_clear_color(res->mod_info->modifier, whandle->plane)) {
1806 bo = res->aux.clear_color_bo;
1807 whandle->offset = res->aux.clear_color_offset;
1809 bo = res->aux.bo;
1810 whandle->stride = res->aux.surf.row_pitch_B;
1811 whandle->offset = res->aux.offset;
1814 whandle->stride = res->surf.row_pitch_B;
1815 bo = res->bo;
1818 whandle->format = res->external_format;
1820 res->mod_info ? res->mod_info->modifier
1821 : tiling_to_modifier(isl_tiling_to_i915_tiling(res->surf.tiling));
1825 usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH ? res->aux.usage :
1826 res->mod_info ? res->mod_info->aux_usage : ISL_AUX_USAGE_NONE;
1828 if (res->aux.usage != allowed_usage) {
1829 enum isl_aux_state aux_state = iris_resource_get_aux_state(res, 0, 0);
1837 iris_gem_set_tiling(bo, &res->surf);
1840 iris_gem_set_tiling(bo, &res->surf);
1854 iris_gem_set_tiling(bo, &res->surf);
1863 struct iris_resource *res)
1865 bool busy = iris_bo_busy(res->bo);
1868 busy |= iris_batch_references(batch, res->bo);
1908 struct iris_resource *res = (void *) resource;
1914 if (res->valid_buffer_range.start > res->valid_buffer_range.end)
1917 if (!resource_is_busy(ice, res)) {
1921 util_range_set_empty(&res->valid_buffer_range);
1928 if (res->bo->gem_handle && res->bo->real.userptr)
1931 struct iris_bo *old_bo = res->bo;
1933 iris_bo_alloc(screen->bufmgr, res->bo->name, resource->width0,
1940 res->bo = new_bo;
1945 screen->vtbl.rebind_buffer(ice, res);
1947 util_range_set_empty(&res->valid_buffer_range);
1995 struct iris_resource *res = (void *) xfer->resource;
2008 .format = res->internal_format,
2115 struct iris_resource *res = (struct iris_resource *) xfer->resource;
2116 struct isl_surf *surf = &res->surf;
2120 uint8_t *tiled_s8_map = res->offset +
2121 iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
2147 struct iris_resource *res = (struct iris_resource *) xfer->resource;
2148 struct isl_surf *surf = &res->surf;
2167 uint8_t *tiled_s8_map = res->offset +
2168 iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
2219 struct iris_resource *res = (struct iris_resource *) xfer->resource;
2220 struct isl_surf *surf = &res->surf;
2225 char *dst = res->offset +
2226 iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
2248 struct iris_resource *res = (struct iris_resource *) xfer->resource;
2249 struct isl_surf *surf = &res->surf;
2269 char *src = res->offset +
2270 iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS);
2293 struct iris_resource *res = (struct iris_resource *) xfer->resource;
2295 void *ptr = res->offset +
2296 iris_bo_map(map->dbg, res->bo, xfer->usage & MAP_FLAGS);
2298 if (res->base.b.target == PIPE_BUFFER) {
2304 struct isl_surf *surf = &res->surf;
2325 can_promote_to_async(const struct iris_resource *res,
2333 return res->base.b.target == PIPE_BUFFER && (usage & PIPE_MAP_WRITE) &&
2335 !util_ranges_intersect(&res->valid_buffer_range, box->x,
2348 struct iris_resource *res = (struct iris_resource *)resource;
2349 struct isl_surf *surf = &res->surf;
2362 can_promote_to_async(res, box, usage)) {
2380 (surf->tiling != ISL_TILING_LINEAR || iris_bo_is_imported(res->bo)))
2387 resource_is_busy(ice, res) ||
2388 iris_has_invalid_primary(res, level, 1, box->z, box->depth);
2416 util_ranges_intersect(&res->valid_buffer_range, box->x,
2420 util_range_add(&res->base.b, &res->valid_buffer_range, box->x, box->x + box->width);
2422 if (iris_bo_mmap_mode(res->bo) != IRIS_MMAP_NONE) {
2432 !iris_has_invalid_primary(res, level, 1, box->z, box->depth)) {
2440 !isl_aux_usage_has_compression(res->aux.usage) &&
2442 iris_bo_mmap_mode(res->bo) != IRIS_MMAP_WB)) {
2448 if (res->surf.tiling == ISL_TILING_4)
2462 iris_resource_access_raw(ice, res, level, box->z, box->depth,
2468 if (iris_batch_references(batch, res->bo))
2492 struct iris_resource *res = (struct iris_resource *) xfer->resource;
2498 if (res->base.b.target == PIPE_BUFFER) {
2499 util_range_add(&res->base.b, &res->valid_buffer_range, box->x, box->x + box->width);
2505 iris_dirty_for_history(ice, res);
2554 struct iris_resource *res = (struct iris_resource *)resource;
2555 const struct isl_surf *surf = &res->surf;
2570 isl_aux_usage_has_compression(res->aux.usage) ||
2571 resource_is_busy(ice, res) ||
2572 iris_bo_mmap_mode(res->bo) == IRIS_MMAP_NONE) {
2579 iris_resource_access_raw(ice, res, level, box->z, box->depth, true);
2582 if (iris_batch_references(batch, res->bo))
2586 uint8_t *dst = iris_bo_map(&ice->dbg, res->bo, MAP_WRITE | MAP_RAW);
2621 struct iris_resource *res)
2623 const uint64_t stages = res->bind_stages;
2627 if (res->bind_history & PIPE_BIND_CONSTANT_BUFFER) {
2639 if (res->bind_history & (PIPE_BIND_SAMPLER_VIEW |
2646 if (res->bind_history & PIPE_BIND_SHADER_BUFFER) {
2652 if (res->bind_history & PIPE_BIND_VERTEX_BUFFER)
2655 if (ice->state.streamout_active && (res->bind_history & PIPE_BIND_STREAM_OUTPUT))
2664 struct iris_resource *res,
2667 if (res->aux.clear_color_unknown ||
2668 memcmp(&res->aux.clear_color, &color, sizeof(color)) != 0) {
2669 res->aux.clear_color = color;
2670 res->aux.clear_color_unknown = false;
2680 struct iris_resource *res = (void *) p_res;
2681 return res->internal_format;