Lines Matching defs:batch
134 struct iris_batch *batch = &ice->batches[q->batch_idx];
141 batch->screen->vtbl.store_data_imm64(batch, bo, offset, true);
145 iris_emit_pipe_control_write(batch, "query: mark available",
154 iris_pipelined_write(struct iris_batch *batch,
159 const struct intel_device_info *devinfo = &batch->screen->devinfo;
164 iris_emit_pipe_control_write(batch, "query: pipelined snapshot write",
172 struct iris_batch *batch = &ice->batches[q->batch_idx];
176 iris_emit_pipe_control_flush(batch,
192 iris_emit_pipe_control_flush(batch,
210 batch->screen->vtbl.store_register_mem64(batch,
217 batch->screen->vtbl.store_register_mem64(batch,
237 batch->screen->vtbl.store_register_mem64(batch, reg, bo, offset, false);
248 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
253 iris_emit_pipe_control_flush(batch,
263 batch->screen->vtbl.store_register_mem64(batch, SO_NUM_PRIMS_WRITTEN(s),
265 batch->screen->vtbl.store_register_mem64(batch, SO_PRIM_STORAGE_NEEDED(s),
557 struct iris_batch *batch = &ice->batches[q->batch_idx];
561 iris_batch_reference_signal_syncobj(batch, &q->syncobj);
579 iris_batch_reference_signal_syncobj(batch, &q->syncobj);
610 return iris_get_monitor_result(ctx, q->monitor, wait, result->batch);
629 struct iris_batch *batch = &ice->batches[q->batch_idx];
630 if (q->syncobj == iris_batch_get_signal_syncobj(batch))
631 iris_batch_flush(batch);
662 struct iris_batch *batch = &ice->batches[q->batch_idx];
663 const struct intel_device_info *devinfo = &batch->screen->devinfo;
678 if (q->syncobj == iris_batch_get_signal_syncobj(batch))
679 iris_batch_flush(batch);
681 batch->screen->vtbl.copy_mem_mem(batch, dst_bo, offset,
697 batch->screen->vtbl.store_data_imm32(batch, dst_bo, offset, q->result);
699 batch->screen->vtbl.store_data_imm64(batch, dst_bo, offset, q->result);
710 mi_builder_init(&b, &batch->screen->devinfo, batch);
712 iris_batch_sync_region_start(batch);
728 iris_batch_sync_region_end(batch);
766 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
769 iris_batch_sync_region_start(batch);
775 iris_emit_pipe_control_flush(batch,
781 mi_builder_init(&b, &batch->screen->devinfo, batch);
806 /* We immediately set the predicate on the render batch, as all the
818 iris_batch_sync_region_end(batch);