Lines Matching refs:ice
65 iris_update_draw_info(struct iris_context *ice,
68 struct iris_screen *screen = (struct iris_screen *)ice->ctx.screen;
72 if (ice->state.prim_mode != info->mode) {
73 ice->state.prim_mode = info->mode;
74 ice->state.dirty |= IRIS_DIRTY_VF_TOPOLOGY;
79 if (points_or_lines != ice->state.prim_is_points_or_lines) {
80 ice->state.prim_is_points_or_lines = points_or_lines;
81 ice->state.dirty |= IRIS_DIRTY_CLIP;
86 ice->state.vertices_per_patch != ice->state.patch_vertices) {
87 ice->state.vertices_per_patch = ice->state.patch_vertices;
88 ice->state.dirty |= IRIS_DIRTY_VF_TOPOLOGY;
92 ice->state.stage_dirty |= IRIS_STAGE_DIRTY_UNCOMPILED_TCS;
96 iris_get_shader_info(ice, MESA_SHADER_TESS_CTRL);
99 ice->state.stage_dirty |= IRIS_STAGE_DIRTY_CONSTANTS_TCS;
100 ice->state.shaders[MESA_SHADER_TESS_CTRL].sysvals_need_upload = true;
106 ice->state.cut_index;
107 if (ice->state.primitive_restart != info->primitive_restart ||
108 ice->state.cut_index != cut_index) {
109 ice->state.dirty |= IRIS_DIRTY_VF;
110 ice->state.cut_index = cut_index;
111 ice->state.dirty |=
112 ((ice->state.primitive_restart != info->primitive_restart) &&
114 ice->state.primitive_restart = info->primitive_restart;
122 iris_update_draw_parameters(struct iris_context *ice,
130 if (ice->state.vs_uses_draw_params) {
131 struct iris_state_ref *draw_params = &ice->draw.draw_params;
139 ice->draw.params_valid = false;
143 if (!ice->draw.params_valid ||
144 ice->draw.params.firstvertex != firstvertex ||
145 ice->draw.params.baseinstance != info->start_instance) {
148 ice->draw.params.firstvertex = firstvertex;
149 ice->draw.params.baseinstance = info->start_instance;
150 ice->draw.params_valid = true;
152 u_upload_data(ice->ctx.const_uploader, 0,
153 sizeof(ice->draw.params), 4, &ice->draw.params,
159 if (ice->state.vs_uses_derived_draw_params) {
160 struct iris_state_ref *derived_params = &ice->draw.derived_draw_params;
163 if (ice->draw.derived_params.drawid != drawid_offset ||
164 ice->draw.derived_params.is_indexed_draw != is_indexed_draw) {
167 ice->draw.derived_params.drawid = drawid_offset;
168 ice->draw.derived_params.is_indexed_draw = is_indexed_draw;
170 u_upload_data(ice->ctx.const_uploader, 0,
171 sizeof(ice->draw.derived_params), 4,
172 &ice->draw.derived_params,
178 ice->state.dirty |= IRIS_DIRTY_VERTEX_BUFFERS |
185 iris_indirect_draw_vbo(struct iris_context *ice,
191 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
204 if (ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT) {
210 const uint64_t orig_dirty = ice->state.dirty;
211 const uint64_t orig_stage_dirty = ice->state.stage_dirty;
216 iris_update_draw_parameters(ice, &info, drawid_offset + i, &indirect, draw);
218 batch->screen->vtbl.upload_render_state(ice, batch, &info, drawid_offset + i, &indirect, draw);
220 ice->state.dirty &= ~IRIS_ALL_DIRTY_FOR_RENDER;
221 ice->state.stage_dirty &= ~IRIS_ALL_STAGE_DIRTY_FOR_RENDER;
227 ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT) {
233 ice->state.dirty = orig_dirty;
234 ice->state.stage_dirty = orig_stage_dirty;
238 iris_simple_draw_vbo(struct iris_context *ice,
244 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
248 iris_update_draw_parameters(ice, draw, drawid_offset, indirect, sc);
250 batch->screen->vtbl.upload_render_state(ice, batch, draw, drawid_offset, indirect, sc);
271 struct iris_context *ice = (struct iris_context *) ctx;
272 struct iris_screen *screen = (struct iris_screen*)ice->ctx.screen;
274 struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER];
276 if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER)
280 ice->state.dirty |= IRIS_ALL_DIRTY_FOR_RENDER;
281 ice->state.stage_dirty |= IRIS_ALL_STAGE_DIRTY_FOR_RENDER;
284 iris_update_draw_info(ice, info);
287 gfx9_toggle_preemption(ice, batch, info);
289 iris_update_compiled_shaders(ice);
291 if (ice->state.dirty & IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES) {
294 if (ice->shaders.prog[stage])
295 iris_predraw_resolve_inputs(ice, batch, draw_aux_buffer_disabled,
298 iris_predraw_resolve_framebuffer(ice, batch, draw_aux_buffer_disabled);
301 if (ice->state.dirty & IRIS_DIRTY_RENDER_MISC_BUFFER_FLUSHES) {
303 iris_predraw_flush_buffers(ice, batch, stage);
306 iris_binder_reserve_3d(ice);
308 batch->screen->vtbl.update_binder_address(batch, &ice->state.binder);
313 iris_indirect_draw_vbo(ice, info, drawid_offset, indirect, &draws[0]);
315 iris_simple_draw_vbo(ice, info, drawid_offset, indirect, &draws[0]);
319 iris_postdraw_update_resolve_tracking(ice, batch);
321 ice->state.dirty &= ~IRIS_ALL_DIRTY_FOR_RENDER;
322 ice->state.stage_dirty &= ~IRIS_ALL_STAGE_DIRTY_FOR_RENDER;
326 iris_update_grid_size_resource(struct iris_context *ice,
329 const struct iris_screen *screen = (void *) ice->ctx.screen;
331 struct iris_state_ref *grid_ref = &ice->state.grid_size;
332 struct iris_state_ref *state_ref = &ice->state.grid_surf_state;
334 const struct iris_compiled_shader *shader = ice->shaders.prog[MESA_SHADER_COMPUTE];
345 memset(ice->state.last_grid, 0, sizeof(ice->state.last_grid));
347 } else if (memcmp(ice->state.last_grid, grid->grid, sizeof(grid->grid)) != 0) {
348 memcpy(ice->state.last_grid, grid->grid, sizeof(grid->grid));
349 u_upload_data(ice->state.dynamic_uploader, 0, sizeof(grid->grid), 4,
365 u_upload_alloc(ice->state.surface_uploader, 0, isl_dev->ss.size,
378 ice->state.stage_dirty |= IRIS_STAGE_DIRTY_BINDINGS_CS;
384 struct iris_context *ice = (struct iris_context *) ctx;
385 struct iris_batch *batch = &ice->batches[IRIS_BATCH_COMPUTE];
387 if (ice->state.predicate == IRIS_PREDICATE_STATE_DONT_RENDER)
391 ice->state.dirty |= IRIS_ALL_DIRTY_FOR_COMPUTE;
392 ice->state.stage_dirty |= IRIS_ALL_STAGE_DIRTY_FOR_COMPUTE;
395 if (ice->state.dirty & IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES)
396 iris_predraw_resolve_inputs(ice, batch, NULL, MESA_SHADER_COMPUTE, false);
398 if (ice->state.dirty & IRIS_DIRTY_COMPUTE_MISC_BUFFER_FLUSHES)
399 iris_predraw_flush_buffers(ice, batch, MESA_SHADER_COMPUTE);
403 iris_update_compiled_compute_shader(ice);
405 if (memcmp(ice->state.last_block, grid->block, sizeof(grid->block)) != 0) {
406 memcpy(ice->state.last_block, grid->block, sizeof(grid->block));
407 ice->state.stage_dirty |= IRIS_STAGE_DIRTY_CONSTANTS_CS;
408 ice->state.shaders[MESA_SHADER_COMPUTE].sysvals_need_upload = true;
411 if (ice->state.last_grid_dim != grid->work_dim) {
412 ice->state.last_grid_dim = grid->work_dim;
413 ice->state.stage_dirty |= IRIS_STAGE_DIRTY_CONSTANTS_CS;
414 ice->state.shaders[MESA_SHADER_COMPUTE].sysvals_need_upload = true;
417 iris_update_grid_size_resource(ice, grid);
419 iris_binder_reserve_compute(ice);
420 batch->screen->vtbl.update_binder_address(batch, &ice->state.binder);
422 if (ice->state.compute_predicate) {
424 ice->state.compute_predicate, 0);
425 ice->state.compute_predicate = NULL;
430 batch->screen->vtbl.upload_compute_state(ice, batch, grid);
434 ice->state.dirty &= ~IRIS_ALL_DIRTY_FOR_COMPUTE;
435 ice->state.stage_dirty &= ~IRIS_ALL_STAGE_DIRTY_FOR_COMPUTE;