Lines Matching defs:cache
145 * cache domain that isn't coherent with it (i.e. the sampler).
148 } cache;
154 * Matrix representation of the cache coherency status of the GPU at the
157 * cache domain j visible to cache domain i (which obviously implies that
158 * coherent_seqnos[i][i] is the most recent flush of cache domain i). This
160 * necessary before accessing data from cache domain i if it was previously
161 * accessed from another cache domain j.
166 * A vector representing the cache coherency status of the L3. For each
167 * cache domain i, l3_coherent_seqnos[i] denotes the seqno of the most
354 * Update the cache coherency status of the batch to reflect a flush of the
370 * Update the cache coherency status of the batch to reflect an invalidation
413 * Update the cache coherency status of the batch to reflect a reset. All