Lines Matching defs:reg
119 #define GET_CHANNEL_SRC(reg, channel) ((reg << (channel * 4)) & (0xf << 20))
122 #define GET_UREG_TYPE(reg) (((reg) >> UREG_TYPE_SHIFT) & REG_TYPE_MASK)
123 #define GET_UREG_NR(reg) (((reg) >> UREG_NR_SHIFT) & REG_NR_MASK)
130 swizzle(int reg, uint32_t x, uint32_t y, uint32_t z, uint32_t w)
136 return ((reg & ~UREG_XYZW_CHANNEL_MASK) |
137 CHANNEL_SRC(GET_CHANNEL_SRC(reg, x), 0) |
138 CHANNEL_SRC(GET_CHANNEL_SRC(reg, y), 1) |
139 CHANNEL_SRC(GET_CHANNEL_SRC(reg, z), 2) |
140 CHANNEL_SRC(GET_CHANNEL_SRC(reg, w), 3));
143 #define A0_DEST(reg) (((reg)&UREG_TYPE_NR_MASK) >> UREG_A0_DEST_SHIFT_LEFT)
144 #define D0_DEST(reg) (((reg)&UREG_TYPE_NR_MASK) >> UREG_A0_DEST_SHIFT_LEFT)
145 #define T0_DEST(reg) (((reg)&UREG_TYPE_NR_MASK) >> UREG_A0_DEST_SHIFT_LEFT)
146 #define A0_SRC0(reg) (((reg)&UREG_MASK) >> UREG_A0_SRC0_SHIFT_LEFT)
147 #define A1_SRC0(reg) (((reg)&UREG_MASK) << UREG_A1_SRC0_SHIFT_RIGHT)
148 #define A1_SRC1(reg) (((reg)&UREG_MASK) >> UREG_A1_SRC1_SHIFT_LEFT)
149 #define A2_SRC1(reg) (((reg)&UREG_MASK) << UREG_A2_SRC1_SHIFT_RIGHT)
150 #define A2_SRC2(reg) (((reg)&UREG_MASK) >> UREG_A2_SRC2_SHIFT_LEFT)
154 #define T0_SAMPLER(reg) (GET_UREG_NR(reg) << T0_SAMPLER_NR_SHIFT)
155 #define T1_ADDRESS_REG(reg) \
156 ((GET_UREG_NR(reg) << T1_ADDRESS_REG_NR_SHIFT) | \
157 (GET_UREG_TYPE(reg) << T1_ADDRESS_REG_TYPE_SHIFT))