Lines Matching refs:screen
130 struct fd_screen *screen = fd_screen(pscreen);
132 if (screen->has_timestamp) {
134 fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n);
135 assert(screen->max_freq > 0);
136 return n * 1000000000 / screen->max_freq;
139 return cpu_time + screen->cpu_gpu_time_delta;
146 struct fd_screen *screen = fd_screen(pscreen);
148 if (screen->tess_bo)
149 fd_bo_del(screen->tess_bo);
151 if (screen->pipe)
152 fd_pipe_del(screen->pipe);
154 if (screen->dev) {
155 fd_device_purge(screen->dev);
156 fd_device_del(screen->dev);
159 if (screen->ro)
160 screen->ro->destroy(screen->ro);
162 fd_bc_fini(&screen->batch_cache);
165 slab_destroy_parent(&screen->transfer_pool);
167 simple_mtx_destroy(&screen->lock);
169 util_idalloc_mt_fini(&screen->buffer_ids);
173 if (screen->compiler)
176 free(screen->perfcntr_queries);
177 free(screen);
187 struct fd_screen *screen = fd_screen(pscreen);
214 return is_a6xx(screen);
219 return is_a2xx(screen);
222 return is_a2xx(screen);
224 return !is_a2xx(screen);
227 return !is_a2xx(screen);
231 return screen->has_robustness;
234 return is_a3xx(screen) || is_a4xx(screen);
237 return has_compute(screen);
248 return screen->primtypes_mask;
264 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) ||
265 is_a6xx(screen);
272 return is_a5xx(screen) || is_a6xx(screen);
275 return is_a6xx(screen);
278 return is_a3xx(screen) || is_a4xx(screen) || is_a6xx(screen);
281 return is_a6xx(screen);
284 return is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
290 if (is_a3xx(screen))
292 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
299 if (is_a3xx(screen))
306 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
314 return is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen);
322 return is_a4xx(screen);
329 if (is_a6xx(screen))
331 else if (is_ir3(screen))
337 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
339 if (is_ir3(screen))
344 if (is_a6xx(screen))
346 if (is_a5xx(screen))
348 if (is_a4xx(screen))
353 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
363 if (fd_device_version(screen->dev) >= FD_VERSION_GMEM_BASE &&
364 is_a6xx(screen))
368 if (is_a6xx(screen))
373 return screen->priority_mask;
376 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
381 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen))
387 if (is_ir3(screen))
398 return is_a6xx(screen) ? 31 : 16;
411 if (is_ir3(screen))
427 return is_a2xx(screen);
454 return !is_a5xx(screen);
458 if (is_ir3(screen))
465 if (is_ir3(screen))
471 return is_a2xx(screen);
474 if (is_ir3(screen))
480 if (is_a6xx(screen) || is_a5xx(screen) || is_a4xx(screen))
485 if (is_a6xx(screen) || is_a5xx(screen) || is_a4xx(screen))
491 if (is_a3xx(screen))
496 return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) ||
497 is_a6xx(screen))
503 return screen->max_rts;
505 return (is_a3xx(screen) || is_a6xx(screen)) ? 1 : 0;
509 return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) ||
510 is_a6xx(screen);
514 return (screen->max_freq > 0) &&
515 (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen));
536 return fd_device_version(screen->dev) >= FD_VERSION_MEMORY_FD;
538 return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD;
540 return screen->has_syncobj;
542 return is_a6xx(screen);
544 return is_a6xx(screen);
597 struct fd_screen *screen = fd_screen(pscreen);
606 if (is_a6xx(screen))
610 if (has_compute(screen))
628 if (shader == PIPE_SHADER_GEOMETRY && is_a6xx(screen))
630 return is_a6xx(screen) ? 32 : 16;
632 return is_a6xx(screen) ? 32 : 16;
640 return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen) ||
641 is_a6xx(screen))
646 return is_ir3(screen) ? 16 : 1;
654 return is_ir3(screen) ? 1 : 0;
666 return is_ir3(screen) ? 1 : 0;
675 (is_a5xx(screen) || is_a6xx(screen)) &&
685 COND(has_compute(screen) && (shader == PIPE_SHADER_COMPUTE),
690 if (is_a4xx(screen) || is_a5xx(screen) || is_a6xx(screen)) {
734 struct fd_screen *screen = fd_screen(pscreen);
737 if (!has_compute(screen))
740 struct ir3_compiler *compiler = screen->compiler;
751 if (screen->gen >= 5)
773 RET((uint64_t[]){screen->ram_size});
783 RET((uint64_t[]){screen->ram_size});
786 RET((uint32_t[]){screen->max_freq / 1000000});
808 struct fd_screen *screen = fd_screen(pscreen);
810 if (is_ir3(screen))
811 return ir3_get_compiler_options(screen->compiler);
819 struct fd_screen *screen = fd_screen(pscreen);
821 if (is_ir3(screen)) {
822 struct ir3_compiler *compiler = screen->compiler;
834 struct fd_screen *screen = fd_screen(pscreen);
841 if (screen->ro) {
861 struct fd_screen *screen = fd_screen(pscreen);
864 max = MIN2(max, screen->num_supported_modifiers);
867 max = screen->num_supported_modifiers;
874 modifiers[num] = screen->supported_modifiers[i];
891 struct fd_screen *screen = fd_screen(pscreen);
894 for (i = 0; i < screen->num_supported_modifiers; i++) {
895 if (modifier == screen->supported_modifiers[i]) {
910 struct fd_screen *screen = fd_screen(pscreen);
914 bo = fd_bo_from_name(screen->dev, whandle->handle);
916 bo = fd_bo_from_handle(screen->dev, whandle->handle, 0);
918 bo = fd_bo_from_dmabuf(screen->dev, whandle->handle);
942 struct fd_screen *screen = fd_screen(pscreen);
944 fd_get_device_uuid(uuid, screen->dev_id);
957 struct fd_screen *screen = CALLOC_STRUCT(fd_screen);
966 if (!screen)
973 pscreen = &screen->base;
975 screen->dev = dev;
976 screen->ro = ro;
977 screen->refcnt = 1;
980 screen->pipe = fd_pipe_new(screen->dev, FD_PIPE_3D);
981 if (!screen->pipe) {
986 if (fd_pipe_get_param(screen->pipe, FD_GMEM_SIZE, &val)) {
990 screen->gmemsize_bytes = env_var_as_unsigned("FD_MESA_GMEM", val);
993 fd_pipe_get_param(screen->pipe, FD_GMEM_BASE, &screen->gmem_base);
996 if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) {
1001 screen->max_freq = 0;
1003 screen->max_freq = val;
1004 if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0)
1005 screen->has_timestamp = true;
1008 screen->dev_id = fd_pipe_dev_id(screen->pipe);
1010 if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) {
1014 screen->gpu_id = val;
1016 if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) {
1019 unsigned core = screen->gpu_id / 100;
1020 unsigned major = (screen->gpu_id % 100) / 10;
1021 unsigned minor = screen->gpu_id % 10;
1026 screen->chip_id = val;
1027 screen->gen = fd_dev_gen(screen->dev_id);
1029 if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) {
1031 screen->priority_mask = 0;
1034 screen->priority_mask = (1 << val) - 1;
1038 screen->has_robustness = true;
1040 screen->has_syncobj = fd_has_syncobj(screen->dev);
1044 NULL, fd_dev_name(screen->dev_id), NULL, 0, NULL, 0);
1048 screen->ram_size = si.totalram;
1051 DBG(" GPU-id: %s", fd_dev_name(screen->dev_id));
1052 DBG(" Chip-id: 0x%016"PRIx64, screen->chip_id);
1053 DBG(" GMEM size: 0x%08x", screen->gmemsize_bytes);
1055 const struct fd_dev_info *info = fd_dev_info(screen->dev_id);
1057 mesa_loge("unsupported GPU: a%03d", screen->gpu_id);
1061 screen->info = info;
1074 switch (screen->gen) {
1091 mesa_loge("unsupported GPU generation: a%uxx", screen->gen);
1096 assert(screen->primtypes);
1097 screen->primtypes_mask = 0;
1099 if (screen->primtypes[i])
1100 screen->primtypes_mask |= (1 << i);
1103 screen->perfcntr_groups =
1104 fd_perfcntrs(screen->dev_id, &screen->num_perfcntr_groups);
1112 screen->reorder = !FD_DBG(INORDER);
1114 fd_bc_init(&screen->batch_cache);
1116 list_inithead(&screen->context_list);
1118 util_idalloc_mt_init_tc(&screen->buffer_ids);
1120 (void)simple_mtx_init(&screen->lock, mtx_plain);
1151 slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16);