Lines Matching refs:rsc
64 struct etna_resource *rsc = etna_resource(prsc);
65 struct etna_resource_level *level = &rsc->levels[ptrans->level];
90 struct etna_resource *rsc = etna_resource(prsc);
91 struct etna_resource_level *level = &rsc->levels[ptrans->level];
106 struct etna_resource *rsc = etna_resource(ptrans->resource);
114 assert(ptrans->level <= rsc->base.last_level);
116 if (rsc->texture && !etna_resource_newer(rsc, etna_resource(rsc->texture)))
117 rsc = etna_resource(rsc->texture); /* switch to using the texture resource */
123 if (trans->rsc)
124 etna_bo_cpu_fini(etna_resource(trans->rsc)->bo);
127 if (trans->rsc) {
131 etna_copy_resource_box(pctx, ptrans->resource, trans->rsc, ptrans->level, &ptrans->box);
134 struct etna_resource_level *res_level = &rsc->levels[ptrans->level];
136 if (rsc->layout == ETNA_LAYOUT_TILED) {
143 ptrans->stride, util_format_get_blocksize(rsc->base.format));
145 } else if (rsc->layout == ETNA_LAYOUT_LINEAR) {
146 util_copy_box(trans->mapped, rsc->base.format, res_level->stride,
153 BUG("unsupported tiling %i", rsc->layout);
159 rsc->seqno++;
161 if (rsc->base.bind & PIPE_BIND_SAMPLER_VIEW) {
174 if (!trans->rsc && !(ptrans->usage & PIPE_MAP_UNSYNCHRONIZED))
175 etna_bo_cpu_fini(rsc->bo);
179 util_range_add(&rsc->base,
180 &rsc->valid_buffer_range,
185 pipe_resource_reference(&trans->rsc, NULL);
199 struct etna_resource *rsc = etna_resource(prsc);
213 !util_ranges_intersect(&rsc->valid_buffer_range,
246 if (rsc->render && etna_resource_newer(etna_resource(rsc->render), rsc) &&
247 (!rsc->texture || etna_resource_newer(etna_resource(rsc->render),
248 etna_resource(rsc->texture)))) {
249 rsc = etna_resource(rsc->render);
252 if (rsc->texture && !etna_resource_newer(rsc, etna_resource(rsc->texture))) {
256 rsc = etna_resource(rsc->texture);
257 } else if (rsc->ts_bo ||
258 (rsc->layout != ETNA_LAYOUT_LINEAR &&
262 rsc->halign != TEXTURE_HALIGN_FOUR)) {
274 if (prsc->depth0 > 1 && rsc->ts_bo) {
284 trans->rsc = etna_resource_alloc(pctx->screen, ETNA_LAYOUT_LINEAR,
286 if (!trans->rsc) {
297 if (rsc->layout & ETNA_LAYOUT_BIT_SUPER) {
314 etna_copy_resource_box(pctx, trans->rsc, &rsc->base, level, &ptrans->box);
317 rsc = etna_resource(trans->rsc);
320 struct etna_resource_level *res_level = &rsc->levels[level];
376 if (trans->rsc || !(usage & PIPE_MAP_UNSYNCHRONIZED)) {
377 enum etna_resource_status status = etna_resource_status(ctx, rsc);
386 if ((trans->rsc && (status & ETNA_PENDING_WRITE)) ||
387 (!trans->rsc &&
406 if (etna_bo_cpu_prep(rsc->bo, prep_flags))
411 trans->mapped = etna_bo_map(rsc->bo);
417 if (rsc->layout == ETNA_LAYOUT_LINEAR) {
450 if (rsc->layout == ETNA_LAYOUT_TILED) {
456 util_format_get_blocksize(rsc->base.format));
458 } else if (rsc->layout == ETNA_LAYOUT_LINEAR) {
459 util_copy_box(trans->staging, rsc->base.format, ptrans->stride,
467 BUG("unsupported tiling %i for reading", rsc->layout);
475 etna_bo_cpu_fini(rsc->bo);
486 struct etna_resource *rsc = etna_resource(ptrans->resource);
489 util_range_add(&rsc->base,
490 &rsc->valid_buffer_range,