Lines Matching refs:screen
134 struct etna_screen *screen = ctx->screen;
153 VIV_FEATURE(screen, chipMinorFeatures2, LINEAR_PE));
172 if (VIV_FEATURE(screen, chipMinorFeatures6, CACHE128B256BPERLINE))
189 if (screen->specs.halti >= 0 && screen->model != 0x880) {
192 assert(screen->specs.pixel_pipes == 1 ||
193 (res->layout & ETNA_LAYOUT_BIT_MULTI) || screen->specs.single_buffer);
194 for (int i = 0; i < screen->specs.pixel_pipes; i++) {
219 if (!screen->specs.v4_compression)
235 VIVS_PS_CONTROL_EXT_OUTPUT_MODE0(translate_output_mode(cbuf->base.format, screen->specs.halti >= 5));
245 cs->PE_COLOR_ADDR = screen->dummy_rt_reloc;
246 for (int i = 0; i < screen->specs.pixel_pipes; i++)
247 cs->PE_PIPE_COLOR_ADDR[i] = screen->dummy_rt_reloc;
274 if (screen->specs.halti >= 0 && screen->model != 0x880) {
275 for (int i = 0; i < screen->specs.pixel_pipes; i++) {
376 else if (screen->specs.single_buffer)
533 struct etna_screen *screen = ctx->screen;
539 if (num_elements > screen->specs.vertex_max_elements) {
541 screen->specs.vertex_max_elements);
565 assert(buffer_idx < screen->specs.stream_count);
581 if (screen->specs.halti < 5) {
715 struct etna_screen *screen = ctx->screen;
717 bool early_z_allowed = !VIV_FEATURE(screen, chipFeatures, NO_EARLY_Z);
735 if (VIV_FEATURE(screen, chipMinorFeatures5, RA_WRITE_DEPTH) &&
768 if (VIV_FEATURE(screen, chipMinorFeatures5, RA_WRITE_DEPTH)) {