Lines Matching refs:screen
87 struct etna_screen *screen = etna_screen(pscreen);
89 if (screen->dummy_desc_reloc.bo)
90 etna_bo_del(screen->dummy_desc_reloc.bo);
92 if (screen->dummy_rt_reloc.bo)
93 etna_bo_del(screen->dummy_rt_reloc.bo);
95 if (screen->perfmon)
96 etna_perfmon_del(screen->perfmon);
100 if (screen->pipe)
101 etna_pipe_del(screen->pipe);
103 if (screen->gpu)
104 etna_gpu_del(screen->gpu);
106 if (screen->ro)
107 screen->ro->destroy(screen->ro);
109 if (screen->dev)
110 etna_device_del(screen->dev);
112 FREE(screen);
142 struct etna_screen *screen = etna_screen(pscreen);
165 return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD;
186 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
189 return !VIV_FEATURE(screen, chipMinorFeatures7, PE_NO_ALPHA_TEST);
208 return screen->specs.stream_count;
210 return VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
218 return screen->specs.max_texture_size;
222 int log2_max_tex_size = util_last_bit(screen->specs.max_texture_size);
234 return screen->specs.seamless_cube_map;
238 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
261 return screen->specs.max_varyings;
276 if (VIV_FEATURE(screen, chipMinorFeatures2, BUG_FIXES8))
279 if (VIV_FEATURE(screen, chipMinorFeatures2, LINE_LOOP))
304 struct etna_screen *screen = etna_screen(pscreen);
323 return util_last_bit(screen->specs.max_texture_size);
339 struct etna_screen *screen = etna_screen(pscreen);
340 bool ubo_enable = screen->specs.halti >= 2;
372 return shader == PIPE_SHADER_FRAGMENT ? screen->specs.max_varyings
373 : screen->specs.vertex_max_elements;
390 return VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
399 return screen->specs.halti >= 2;
403 ? screen->specs.fragment_sampler_count
404 : screen->specs.vertex_sampler_count;
411 ? screen->specs.max_ps_uniforms * sizeof(float[4])
412 : screen->specs.max_vs_uniforms * sizeof(float[4]);
439 gpu_supports_texture_target(struct etna_screen *screen,
446 if (screen->specs.halti < 0 &&
456 gpu_supports_texture_format(struct etna_screen *screen, uint32_t fmt,
462 supported = VIV_FEATURE(screen, chipFeatures, ETC1_TEXTURE_COMPRESSION);
465 supported = VIV_FEATURE(screen, chipFeatures, DXT_TEXTURE_COMPRESSION);
468 supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
471 supported = VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
474 supported = screen->specs.tex_astc;
478 supported = VIV_FEATURE(screen, chipMinorFeatures2, HALTI1);
482 supported = VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
489 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
495 gpu_supports_render_format(struct etna_screen *screen, enum pipe_format format,
508 return VIV_FEATURE(screen, chipMinorFeatures5, HALTI5);
512 return VIV_FEATURE(screen, chipMinorFeatures5, HALTI5);
515 return VIV_FEATURE(screen, chipMinorFeatures5, HALTI3);
518 return VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
521 return VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
525 return VIV_FEATURE(screen, chipMinorFeatures1, HALTI0);
531 gpu_supports_vertex_format(struct etna_screen *screen, enum pipe_format format)
537 return VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
550 struct etna_screen *screen = etna_screen(pscreen);
553 if (!gpu_supports_texture_target(screen, target))
560 if (gpu_supports_render_format(screen, format, sample_count))
572 if (!gpu_supports_texture_format(screen, fmt, format))
580 if (gpu_supports_vertex_format(screen, format))
588 VIV_FEATURE(screen, chipFeatures, 32_BIT_INDICES))) {
616 struct etna_screen *screen = etna_screen(pscreen);
619 if ((screen->specs.pixel_pipes == 1 || screen->specs.single_buffer) &&
680 etna_determine_uniform_limits(struct etna_screen *screen)
686 if (screen->model == chipModel_GC2000 &&
687 (screen->revision == 0x5118 || screen->revision == 0x5140)) {
688 screen->specs.max_vs_uniforms = 256;
689 screen->specs.max_ps_uniforms = 64;
690 } else if (screen->specs.num_constants == 320) {
691 screen->specs.max_vs_uniforms = 256;
692 screen->specs.max_ps_uniforms = 64;
693 } else if (screen->specs.num_constants > 256 &&
694 screen->model == chipModel_GC1000) {
696 screen->specs.max_vs_uniforms = 256;
697 screen->specs.max_ps_uniforms = 64;
698 } else if (screen->specs.num_constants > 256) {
699 screen->specs.max_vs_uniforms = 256;
700 screen->specs.max_ps_uniforms = 256;
701 } else if (screen->specs.num_constants == 256) {
702 screen->specs.max_vs_uniforms = 256;
703 screen->specs.max_ps_uniforms = 256;
705 screen->specs.max_vs_uniforms = 168;
706 screen->specs.max_ps_uniforms = 64;
711 etna_determine_sampler_limits(struct etna_screen *screen)
714 if (screen->specs.halti >= 1) {
715 screen->specs.vertex_sampler_offset = 16;
716 screen->specs.fragment_sampler_count = 16;
717 screen->specs.vertex_sampler_count = 16;
719 screen->specs.vertex_sampler_offset = 8;
720 screen->specs.fragment_sampler_count = 8;
721 screen->specs.vertex_sampler_count = 4;
724 if (screen->model == 0x400)
725 screen->specs.vertex_sampler_count = 0;
729 etna_get_specs(struct etna_screen *screen)
734 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_INSTRUCTION_COUNT, &val)) {
740 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE,
745 screen->specs.vertex_output_buffer_size = val;
747 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_VERTEX_CACHE_SIZE, &val)) {
751 screen->specs.vertex_cache_size = val;
753 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_SHADER_CORE_COUNT, &val)) {
757 screen->specs.shader_core_count = val;
759 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_STREAM_COUNT, &val)) {
763 screen->specs.stream_count = val;
765 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REGISTER_MAX, &val)) {
769 screen->specs.max_registers = val;
771 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_PIXEL_PIPES, &val)) {
775 screen->specs.pixel_pipes = val;
777 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) {
785 screen->specs.num_constants = val;
787 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_VARYINGS, &val)) {
791 screen->specs.max_varyings = MAX2(val, ETNA_NUM_VARYINGS);
795 if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI5))
796 screen->specs.halti = 5; /* New GC7000/GC8x00 */
797 else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI4))
798 screen->specs.halti = 4; /* Old GC7000/GC7400 */
799 else if (VIV_FEATURE(screen, chipMinorFeatures5, HALTI3))
800 screen->specs.halti = 3; /* None? */
801 else if (VIV_FEATURE(screen, chipMinorFeatures4, HALTI2))
802 screen->specs.halti = 2; /* GC2500/GC3000/GC5000/GC6400 */
803 else if (VIV_FEATURE(screen, chipMinorFeatures2, HALTI1))
804 screen->specs.halti = 1; /* GC900/GC4000/GC7000UL */
805 else if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0))
806 screen->specs.halti = 0; /* GC880/GC2000/GC7000TM */
808 screen->specs.halti = -1; /* GC7000nanolite / pre-GC2000 except GC880 */
809 if (screen->specs.halti >= 0)
810 DBG("etnaviv: GPU arch: HALTI%d", screen->specs.halti);
814 screen->specs.can_supertile =
815 VIV_FEATURE(screen, chipMinorFeatures0, SUPER_TILED);
816 screen->specs.bits_per_tile =
817 !VIV_FEATURE(screen, chipMinorFeatures0, 2BITPERTILE) ||
818 VIV_FEATURE(screen, chipMinorFeatures6, CACHE128B256BPERLINE) ? 4 : 2;
820 screen->specs.ts_clear_value =
821 VIV_FEATURE(screen, chipMinorFeatures10, DEC400) ? 0xffffffff :
822 screen->specs.bits_per_tile == 4 ? 0x11111111 : 0x55555555;
824 screen->specs.vs_need_z_div =
825 screen->model < 0x1000 && screen->model != 0x880;
826 screen->specs.has_sin_cos_sqrt =
827 VIV_FEATURE(screen, chipMinorFeatures0, HAS_SQRT_TRIG);
828 screen->specs.has_sign_floor_ceil =
829 VIV_FEATURE(screen, chipMinorFeatures0, HAS_SIGN_FLOOR_CEIL);
830 screen->specs.has_shader_range_registers =
831 screen->model >= 0x1000 || screen->model == 0x880;
832 screen->specs.npot_tex_any_wrap =
833 VIV_FEATURE(screen, chipMinorFeatures1, NON_POWER_OF_TWO);
834 screen->specs.has_new_transcendentals =
835 VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS);
836 screen->specs.has_halti2_instructions =
837 VIV_FEATURE(screen, chipMinorFeatures4, HALTI2);
838 screen->specs.has_no_oneconst_limit =
839 VIV_FEATURE(screen, chipMinorFeatures8, SH_NO_ONECONST_LIMIT);
840 screen->specs.v4_compression =
841 VIV_FEATURE(screen, chipMinorFeatures6, V4_COMPRESSION);
842 screen->specs.seamless_cube_map =
843 (screen->model != 0x880) && /* Seamless cubemap is broken on GC880? */
844 VIV_FEATURE(screen, chipMinorFeatures2, SEAMLESS_CUBE_MAP);
846 if (screen->specs.halti >= 5) {
848 screen->specs.vs_offset = 0;
849 screen->specs.ps_offset = 0;
850 screen->specs.max_instructions = 0; /* Do not program shaders manually */
851 screen->specs.has_icache = true;
852 } else if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) {
859 screen->specs.vs_offset = 0xC000;
864 screen->specs.ps_offset = 0x8000 + 0x1000;
865 screen->specs.max_instructions = 256; /* maximum number instructions for non-icache use */
866 screen->specs.has_icache = true;
869 screen->specs.vs_offset = 0xC000;
870 screen->specs.ps_offset = 0xD000; /* like vivante driver */
871 screen->specs.max_instructions = 256;
873 screen->specs.vs_offset = 0x4000;
874 screen->specs.ps_offset = 0x6000;
875 screen->specs.max_instructions = instruction_count;
877 screen->specs.has_icache = false;
880 if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) {
881 screen->specs.vertex_max_elements = 16;
886 screen->specs.vertex_max_elements = 10;
889 etna_determine_uniform_limits(screen);
890 etna_determine_sampler_limits(screen);
892 if (screen->specs.halti >= 5) {
893 screen->specs.has_unified_uniforms = true;
894 screen->specs.vs_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS_MIRROR(0);
895 screen->specs.ps_uniforms_offset = VIVS_SH_HALTI5_UNIFORMS(screen->specs.max_vs_uniforms*4);
896 } else if (screen->specs.halti >= 1) {
899 screen->specs.has_unified_uniforms = true;
900 screen->specs.vs_uniforms_offset = VIVS_SH_UNIFORMS(0);
905 screen->specs.ps_uniforms_offset = VIVS_SH_UNIFORMS(screen->specs.max_vs_uniforms*4);
907 screen->specs.has_unified_uniforms = false;
908 screen->specs.vs_uniforms_offset = VIVS_VS_UNIFORMS(0);
909 screen->specs.ps_uniforms_offset = VIVS_PS_UNIFORMS(0);
912 screen->specs.max_texture_size =
913 VIV_FEATURE(screen, chipMinorFeatures0, TEXTURE_8K) ? 8192 : 2048;
914 screen->specs.max_rendertarget_size =
915 VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048;
917 screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER);
918 if (screen->specs.single_buffer)
919 DBG("etnaviv: Single buffer mode enabled with %d pixel pipes", screen->specs.pixel_pipes);
921 screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC) &&
922 !VIV_FEATURE(screen, chipMinorFeatures6, NO_ASTC);
924 screen->specs.use_blt = VIV_FEATURE(screen, chipMinorFeatures5, BLT_ENGINE);
929 if (!VIV_FEATURE(screen, chipMinorFeatures0, MC20))
930 screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR;
942 struct etna_screen *screen = etna_screen(pscreen);
946 bo = etna_bo_from_name(screen->dev, whandle->handle);
948 bo = etna_bo_from_dmabuf(screen->dev, whandle->handle);
972 struct etna_screen *screen = etna_screen(pscreen);
973 struct etna_compiler *compiler = screen->compiler;
982 struct etna_screen *screen = CALLOC_STRUCT(etna_screen);
986 if (!screen)
989 pscreen = &screen->base;
990 screen->dev = dev;
991 screen->gpu = gpu;
992 screen->ro = ro;
993 screen->refcnt = 1;
995 screen->drm_version = etnaviv_device_version(screen->dev);
1001 screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D);
1002 if (!screen->pipe) {
1007 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_MODEL, &val)) {
1011 screen->model = val;
1013 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_REVISION, &val)) {
1017 screen->revision = val;
1019 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_0, &val)) {
1023 screen->features[0] = val;
1025 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_1, &val)) {
1029 screen->features[1] = val;
1031 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_2, &val)) {
1035 screen->features[2] = val;
1037 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_3, &val)) {
1041 screen->features[3] = val;
1043 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_4, &val)) {
1047 screen->features[4] = val;
1049 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_5, &val)) {
1053 screen->features[5] = val;
1055 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_6, &val)) {
1059 screen->features[6] = val;
1061 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_7, &val)) {
1065 screen->features[7] = val;
1067 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_8, &val)) {
1071 screen->features[8] = val;
1073 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_9, &val)) {
1077 screen->features[9] = val;
1079 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_10, &val)) {
1083 screen->features[10] = val;
1085 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_11, &val)) {
1089 screen->features[11] = val;
1091 if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_12, &val)) {
1095 screen->features[12] = val;
1097 if (!etna_get_specs(screen))
1100 if (screen->specs.halti >= 5 && !etnaviv_device_softpin_capable(dev)) {
1107 screen->features[viv_chipFeatures] |= chipFeatures_NO_EARLY_Z;
1109 screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR;
1111 screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE;
1113 screen->specs.can_supertile = 0;
1115 screen->specs.single_buffer = 0;
1117 screen->features[viv_chipMinorFeatures2] &= ~chipMinorFeatures2_LINEAR_PE;
1143 util_dynarray_init(&screen->supported_pm_queries, NULL);
1144 slab_create_parent(&screen->transfer_pool, sizeof(struct etna_transfer), 16);
1146 if (screen->drm_version >= ETNA_DRM_VERSION_PERFMON)
1147 etna_pm_query_setup(screen);
1151 screen->dummy_rt_reloc.bo = etna_bo_new(screen->dev, 64 * 64 * 4,
1153 if (!screen->dummy_rt_reloc.bo)
1156 screen->dummy_rt_reloc.offset = 0;
1157 screen->dummy_rt_reloc.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
1159 if (screen->specs.halti >= 5) {
1163 screen->dummy_desc_reloc.bo = etna_bo_new(screen->dev, 0x100,
1165 if (!screen->dummy_desc_reloc.bo)
1168 buf = etna_bo_map(screen->dummy_desc_reloc.bo);
1169 etna_bo_cpu_prep(screen->dummy_desc_reloc.bo, DRM_ETNA_PREP_WRITE);
1171 etna_bo_cpu_fini(screen->dummy_desc_reloc.bo);
1172 screen->dummy_desc_reloc.offset = 0;
1173 screen->dummy_desc_reloc.flags = ETNA_RELOC_READ;