Lines Matching defs:width
92 if (rs->width & ETNA_RS_WIDTH_MASK)
142 cs->RS_WINDOW_SIZE = VIVS_RS_WINDOW_SIZE_WIDTH(rs->width) |
147 cs->RS_WINDOW_SIZE = VIVS_RS_WINDOW_SIZE_WIDTH(rs->width) |
301 /* use tiled clear if width is multiple of 16 */
314 .width = surf->surf.padded_width, /* These must be padded to 16x4 if !LINEAR, otherwise RS will hang */
501 memcpy(drow, srow, tile_size * blit_info->src.box.width);
608 /* The width/height are in pixels; they do not change as a result of
610 * to a non-multisampled surface, the width and height will be
612 if (blit_info->dst.box.width != blit_info->src.box.width ||
615 blit_info->src.box.width, blit_info->src.box.height,
616 blit_info->dst.box.width, blit_info->dst.box.height);
658 /* we may be given coordinates up to the padded width to avoid
660 assert((blit_info->src.box.x + blit_info->src.box.width) * msaa_xscale <= src_lev->padded_width);
662 assert(blit_info->dst.box.x + blit_info->dst.box.width <= dst_lev->padded_width);
684 /* If the width is not aligned to the RS width, but is within our
685 * padding, adjust the width to suite the RS width restriction.
686 * Note: the RS width/height are converted to source samples here. */
687 unsigned int width = blit_info->src.box.width * msaa_xscale;
692 if (width & (w_align - 1) && width >= src_lev->width * msaa_xscale && width >= dst_lev->width)
693 width = align(width, w_align);
699 if (width > src_lev->padded_width ||
700 width > dst_lev->padded_width * msaa_xscale ||
703 width & (w_align - 1) || height & (h_align - 1))
786 .width = width,
820 * width/height), format conversion, mask and filter and even a scissor rectangle