Lines Matching defs:stream
49 CMD_STALL(struct etna_cmd_stream *stream, uint32_t from, uint32_t to)
51 etna_cmd_stream_emit(stream, VIV_FE_STALL_HEADER_OP_STALL);
52 etna_cmd_stream_emit(stream, VIV_FE_STALL_TOKEN_FROM(from) | VIV_FE_STALL_TOKEN_TO(to));
56 etna_stall(struct etna_cmd_stream *stream, uint32_t from, uint32_t to)
59 etna_cmd_stream_reserve(stream, blt ? 8 : 4);
62 etna_emit_load_state(stream, VIVS_BLT_ENABLE >> 2, 1, 0);
63 etna_cmd_stream_emit(stream, 1);
67 etna_emit_load_state(stream, VIVS_GL_SEMAPHORE_TOKEN >> 2, 1, 0);
68 etna_cmd_stream_emit(stream, VIVS_GL_SEMAPHORE_TOKEN_FROM(from) | VIVS_GL_SEMAPHORE_TOKEN_TO(to));
72 CMD_STALL(stream, from, to);
75 etna_emit_load_state(stream, VIVS_GL_STALL_TOKEN >> 2, 1, 0);
76 etna_cmd_stream_emit(stream, VIVS_GL_STALL_TOKEN_FROM(from) | VIVS_GL_STALL_TOKEN_TO(to));
80 etna_emit_load_state(stream, VIVS_BLT_ENABLE >> 2, 1, 0);
81 etna_cmd_stream_emit(stream, 0);
86 etna_coalsence_emit(stream, &coalesce, VIVS_##state_name, src_value)
89 etna_coalsence_emit_fixp(stream, &coalesce, VIVS_##state_name, src_value)
92 etna_coalsence_emit_reloc(stream, &coalesce, VIVS_##state_name, src_value)
128 struct etna_cmd_stream *stream = ctx->stream;
132 etna_coalesce_start(stream, &coalesce);
155 etna_coalesce_end(stream, &coalesce);
162 struct etna_cmd_stream *stream = ctx->stream;
166 etna_coalesce_start(stream, &coalesce);
210 etna_coalesce_end(stream, &coalesce);
220 struct etna_cmd_stream *stream = ctx->stream;
228 etna_cmd_stream_reserve(stream, required_stream_size(ctx));
246 etna_set_state(stream, VIVS_GL_FLUSH_CACHE, to_flush);
247 etna_stall(stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
252 etna_set_state(stream, VIVS_TS_FLUSH_CACHE, VIVS_TS_FLUSH_CACHE_FLUSH);
260 /*17800*/ etna_set_state_multi(stream, VIVS_NFE_GENERIC_ATTRIB_CONFIG0(0),
263 /*17A00*/ etna_set_state_multi(stream, VIVS_NFE_GENERIC_ATTRIB_SCALE(0),
266 /*17A80*/ etna_set_state_multi(stream, VIVS_NFE_GENERIC_ATTRIB_CONFIG1(0),
271 /*00600*/ etna_set_state_multi(stream, VIVS_FE_VERTEX_ELEMENT_CONFIG(0),
275 /*00780*/ etna_set_state_multi(stream, VIVS_FE_GENERIC_ATTRIB_SCALE(0),
305 etna_coalesce_start(stream, &coalesce);
346 } else { /* hw w/ single vertex stream */
530 etna_coalesce_end(stream, &coalesce);
547 etna_stall(ctx->stream, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE);
580 etna_set_state(stream, VIVS_VS_NEWRANGE_LOW, 0);
581 etna_set_state(stream, VIVS_VS_NEWRANGE_HIGH, ctx->shader_state.vs_inst_mem_size / 4);
583 etna_set_state_reloc(stream, VIVS_VS_INST_ADDR, &ctx->shader_state.VS_INST_ADDR);
584 etna_set_state(stream, VIVS_SH_CONFIG, 0x00000002);
585 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, VIVS_VS_ICACHE_CONTROL_ENABLE);
586 etna_set_state(stream, VIVS_VS_ICACHE_COUNT, ctx->shader_state.vs_inst_mem_size / 4 - 1);
589 etna_set_state(stream, VIVS_PS_NEWRANGE_LOW, 0);
590 etna_set_state(stream, VIVS_PS_NEWRANGE_HIGH, ctx->shader_state.ps_inst_mem_size / 4);
592 etna_set_state_reloc(stream, VIVS_PS_INST_ADDR, &ctx->shader_state.PS_INST_ADDR);
593 etna_set_state(stream, VIVS_SH_CONFIG, 0x00000002);
594 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL, VIVS_VS_ICACHE_CONTROL_ENABLE);
595 etna_set_state(stream, VIVS_PS_ICACHE_COUNT, ctx->shader_state.ps_inst_mem_size / 4 - 1);
601 etna_set_state(stream, VIVS_VS_RANGE, (ctx->shader_state.vs_inst_mem_size / 4 - 1) << 16);
602 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL,
606 etna_set_state_reloc(stream, VIVS_VS_INST_ADDR, &ctx->shader_state.VS_INST_ADDR);
609 etna_set_state(stream, VIVS_PS_RANGE, (ctx->shader_state.ps_inst_mem_size / 4 - 1) << 16);
610 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL,
614 etna_set_state_reloc(stream, VIVS_PS_INST_ADDR, &ctx->shader_state.PS_INST_ADDR);
619 etna_set_state(stream, VIVS_VS_ICACHE_CONTROL,
624 etna_set_state(stream, VIVS_VS_RANGE, (ctx->shader_state.vs_inst_mem_size / 4 - 1) << 16);
625 etna_set_state(stream, VIVS_PS_RANGE, ((ctx->shader_state.ps_inst_mem_size / 4 - 1 + 0x100) << 16) |
628 etna_set_state_multi(stream, screen->specs.vs_offset,
631 etna_set_state_multi(stream, screen->specs.ps_offset,
637 etna_set_state(stream, VIVS_VS_UNIFORM_BASE, 0);
638 etna_set_state(stream, VIVS_PS_UNIFORM_BASE, screen->specs.max_vs_uniforms);
642 etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH);
647 etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH | VIVS_VS_UNIFORM_CACHE_PS);
653 etna_set_state(stream, VIVS_VS_ICACHE_PREFETCH, 0x00000000);
654 etna_set_state(stream, VIVS_PS_ICACHE_PREFETCH, 0x00000000);
655 etna_stall(stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
660 etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH);
667 etna_set_state(stream, VIVS_VS_UNIFORM_CACHE, VIVS_VS_UNIFORM_CACHE_FLUSH | VIVS_VS_UNIFORM_CACHE_PS);