Lines Matching refs:stream
108 emit_blt_clearimage(struct etna_cmd_stream *stream, const struct blt_clear_op *op)
110 etna_cmd_stream_reserve(stream, 64*2); /* Make sure BLT op doesn't get broken up */
112 etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000001);
114 etna_set_state(stream, VIVS_BLT_CONFIG, VIVS_BLT_CONFIG_CLEAR_BPP(op->dest.bpp-1));
119 etna_set_state(stream, VIVS_BLT_DEST_STRIDE, blt_compute_stride_bits(&op->dest));
120 etna_set_state(stream, VIVS_BLT_DEST_CONFIG, blt_compute_img_config_bits(&op->dest, true));
121 etna_set_state_reloc(stream, VIVS_BLT_DEST_ADDR, &op->dest.addr);
122 etna_set_state(stream, VIVS_BLT_SRC_STRIDE, blt_compute_stride_bits(&op->dest));
123 etna_set_state(stream, VIVS_BLT_SRC_CONFIG, blt_compute_img_config_bits(&op->dest, false));
124 etna_set_state_reloc(stream, VIVS_BLT_SRC_ADDR, &op->dest.addr);
125 etna_set_state(stream, VIVS_BLT_DEST_POS, VIVS_BLT_DEST_POS_X(op->rect_x) | VIVS_BLT_DEST_POS_Y(op->rect_y));
126 etna_set_state(stream, VIVS_BLT_IMAGE_SIZE, VIVS_BLT_IMAGE_SIZE_WIDTH(op->rect_w) | VIVS_BLT_IMAGE_SIZE_HEIGHT(op->rect_h));
127 etna_set_state(stream, VIVS_BLT_CLEAR_COLOR0, op->clear_value[0]);
128 etna_set_state(stream, VIVS_BLT_CLEAR_COLOR1, op->clear_value[1]);
129 etna_set_state(stream, VIVS_BLT_CLEAR_BITS0, op->clear_bits[0]);
130 etna_set_state(stream, VIVS_BLT_CLEAR_BITS1, op->clear_bits[1]);
132 etna_set_state_reloc(stream, VIVS_BLT_DEST_TS, &op->dest.ts_addr);
133 etna_set_state_reloc(stream, VIVS_BLT_SRC_TS, &op->dest.ts_addr);
134 etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE0, op->dest.ts_clear_value[0]);
135 etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE1, op->dest.ts_clear_value[1]);
136 etna_set_state(stream, VIVS_BLT_SRC_TS_CLEAR_VALUE0, op->dest.ts_clear_value[0]);
137 etna_set_state(stream, VIVS_BLT_SRC_TS_CLEAR_VALUE1, op->dest.ts_clear_value[1]);
139 etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
140 etna_set_state(stream, VIVS_BLT_COMMAND, VIVS_BLT_COMMAND_COMMAND_CLEAR_IMAGE);
141 etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
142 etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000000);
147 emit_blt_copyimage(struct etna_cmd_stream *stream, const struct blt_imgcopy_op *op)
149 etna_cmd_stream_reserve(stream, 64*2); /* Never allow BLT sequences to be broken up */
151 etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000001);
152 etna_set_state(stream, VIVS_BLT_CONFIG,
155 etna_set_state(stream, VIVS_BLT_SRC_STRIDE, blt_compute_stride_bits(&op->src));
156 etna_set_state(stream, VIVS_BLT_SRC_CONFIG, blt_compute_img_config_bits(&op->src, false));
157 etna_set_state(stream, VIVS_BLT_SWIZZLE,
160 etna_set_state(stream, VIVS_BLT_UNK140A0, 0x00040004);
161 etna_set_state(stream, VIVS_BLT_UNK1409C, 0x00400040);
163 etna_set_state_reloc(stream, VIVS_BLT_SRC_TS, &op->src.ts_addr);
164 etna_set_state(stream, VIVS_BLT_SRC_TS_CLEAR_VALUE0, op->src.ts_clear_value[0]);
165 etna_set_state(stream, VIVS_BLT_SRC_TS_CLEAR_VALUE1, op->src.ts_clear_value[1]);
167 etna_set_state_reloc(stream, VIVS_BLT_SRC_ADDR, &op->src.addr);
168 etna_set_state(stream, VIVS_BLT_DEST_STRIDE, blt_compute_stride_bits(&op->dest));
169 etna_set_state(stream, VIVS_BLT_DEST_CONFIG,
174 etna_set_state_reloc(stream, VIVS_BLT_DEST_TS, &op->dest.ts_addr);
175 etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE0, op->dest.ts_clear_value[0]);
176 etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE1, op->dest.ts_clear_value[1]);
178 etna_set_state_reloc(stream, VIVS_BLT_DEST_ADDR, &op->dest.addr);
179 etna_set_state(stream, VIVS_BLT_SRC_POS, VIVS_BLT_DEST_POS_X(op->src_x) | VIVS_BLT_DEST_POS_Y(op->src_y));
180 etna_set_state(stream, VIVS_BLT_DEST_POS, VIVS_BLT_DEST_POS_X(op->dest_x) | VIVS_BLT_DEST_POS_Y(op->dest_y));
181 etna_set_state(stream, VIVS_BLT_IMAGE_SIZE, VIVS_BLT_IMAGE_SIZE_WIDTH(op->rect_w) | VIVS_BLT_IMAGE_SIZE_HEIGHT(op->rect_h));
182 etna_set_state(stream, VIVS_BLT_UNK14058, 0xffffffff);
183 etna_set_state(stream, VIVS_BLT_UNK1405C, 0xffffffff);
184 etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
185 etna_set_state(stream, VIVS_BLT_COMMAND, VIVS_BLT_COMMAND_COMMAND_COPY_IMAGE);
186 etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
187 etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000000);
192 emit_blt_inplace(struct etna_cmd_stream *stream, const struct blt_inplace_op *op)
195 etna_cmd_stream_reserve(stream, 64*2); /* Never allow BLT sequences to be broken up */
196 etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000001);
197 etna_set_state(stream, VIVS_BLT_CONFIG,
201 etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE0, op->ts_clear_value[0]);
202 etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE1, op->ts_clear_value[1]);
203 etna_set_state_reloc(stream, VIVS_BLT_DEST_ADDR, &op->addr);
204 etna_set_state_reloc(stream, VIVS_BLT_DEST_TS, &op->ts_addr);
205 etna_set_state(stream, 0x14068, op->num_tiles);
206 etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
207 etna_set_state(stream, VIVS_BLT_COMMAND, 0x00000004);
208 etna_set_state(stream, VIVS_BLT_SET_COMMAND, 0x00000003);
209 etna_set_state(stream, VIVS_BLT_ENABLE, 0x00000000);
249 emit_blt_clearimage(ctx->stream, &clr);
328 emit_blt_clearimage(ctx->stream, &clr);
347 etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE, 0x00000c23);
348 etna_set_state(ctx->stream, VIVS_TS_FLUSH_CACHE, VIVS_TS_FLUSH_CACHE_FLUSH);
360 etna_stall(ctx->stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_BLT);
363 etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE, 0x00000c23);
365 etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE, 0x00000002);
454 etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE, 0x00000c23);
455 etna_set_state(ctx->stream, VIVS_TS_FLUSH_CACHE, 0x00000001);
456 emit_blt_inplace(ctx->stream, &op);
511 etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE, 0x00000c23);
512 etna_set_state(ctx->stream, VIVS_TS_FLUSH_CACHE, 0x00000001);
513 emit_blt_copyimage(ctx->stream, &op);
519 etna_stall(ctx->stream, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_BLT);
520 etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE, 0x00000c23);