Lines Matching refs:dest
113 assert(op->dest.bpp);
114 etna_set_state(stream, VIVS_BLT_CONFIG, VIVS_BLT_CONFIG_CLEAR_BPP(op->dest.bpp-1));
115 /* NB: blob sets format to 1 in dest/src config for clear, and the swizzle to RRRR.
119 etna_set_state(stream, VIVS_BLT_DEST_STRIDE, blt_compute_stride_bits(&op->dest));
120 etna_set_state(stream, VIVS_BLT_DEST_CONFIG, blt_compute_img_config_bits(&op->dest, true));
121 etna_set_state_reloc(stream, VIVS_BLT_DEST_ADDR, &op->dest.addr);
122 etna_set_state(stream, VIVS_BLT_SRC_STRIDE, blt_compute_stride_bits(&op->dest));
123 etna_set_state(stream, VIVS_BLT_SRC_CONFIG, blt_compute_img_config_bits(&op->dest, false));
124 etna_set_state_reloc(stream, VIVS_BLT_SRC_ADDR, &op->dest.addr);
131 if (op->dest.use_ts) {
132 etna_set_state_reloc(stream, VIVS_BLT_DEST_TS, &op->dest.ts_addr);
133 etna_set_state_reloc(stream, VIVS_BLT_SRC_TS, &op->dest.ts_addr);
134 etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE0, op->dest.ts_clear_value[0]);
135 etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE1, op->dest.ts_clear_value[1]);
136 etna_set_state(stream, VIVS_BLT_SRC_TS_CLEAR_VALUE0, op->dest.ts_clear_value[0]);
137 etna_set_state(stream, VIVS_BLT_SRC_TS_CLEAR_VALUE1, op->dest.ts_clear_value[1]);
154 VIVS_BLT_CONFIG_DEST_ENDIAN(op->dest.endian_mode));
159 blt_compute_swizzle_bits(&op->dest, true));
168 etna_set_state(stream, VIVS_BLT_DEST_STRIDE, blt_compute_stride_bits(&op->dest));
170 blt_compute_img_config_bits(&op->dest, true) |
172 assert(!op->dest.use_ts); /* Dest TS path doesn't work for copies? */
173 if (op->dest.use_ts) {
174 etna_set_state_reloc(stream, VIVS_BLT_DEST_TS, &op->dest.ts_addr);
175 etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE0, op->dest.ts_clear_value[0]);
176 etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE1, op->dest.ts_clear_value[1]);
178 etna_set_state_reloc(stream, VIVS_BLT_DEST_ADDR, &op->dest.addr);
222 clr.dest.addr.bo = res->bo;
223 clr.dest.addr.offset = surf->surf.offset;
224 clr.dest.addr.flags = ETNA_RELOC_WRITE;
225 clr.dest.bpp = util_format_get_blocksize(surf->base.format);
226 clr.dest.stride = surf->surf.stride;
227 clr.dest.tiling = res->layout;
230 clr.dest.use_ts = 1;
231 clr.dest.ts_addr.bo = res->ts_bo;
232 clr.dest.ts_addr.offset = surf->level->ts_offset;
233 clr.dest.ts_addr.flags = ETNA_RELOC_WRITE;
234 clr.dest.ts_clear_value[0] = new_clear_value;
235 clr.dest.ts_clear_value[1] = new_clear_value >> 32;
236 clr.dest.ts_mode = surf->level->ts_mode;
237 clr.dest.ts_compress_fmt = surf->level->ts_compress_fmt;
301 clr.dest.addr.bo = res->bo;
302 clr.dest.addr.offset = surf->surf.offset;
303 clr.dest.addr.flags = ETNA_RELOC_WRITE;
304 clr.dest.bpp = util_format_get_blocksize(surf->base.format);
305 clr.dest.stride = surf->surf.stride;
306 clr.dest.tiling = res->layout;
309 clr.dest.use_ts = 1;
310 clr.dest.ts_addr.bo = res->ts_bo;
311 clr.dest.ts_addr.offset = surf->level->ts_offset;
312 clr.dest.ts_addr.flags = ETNA_RELOC_WRITE;
313 clr.dest.ts_clear_value[0] = surf->level->clear_value;
314 clr.dest.ts_clear_value[1] = surf->level->clear_value;
315 clr.dest.ts_mode = surf->level->ts_mode;
316 clr.dest.ts_compress_fmt = surf->level->ts_compress_fmt;
481 op.dest.addr.bo = dst->bo;
482 op.dest.addr.offset = dst_lev->offset + blit_info->dst.box.z * dst_lev->layer_stride;
483 op.dest.addr.flags = ETNA_RELOC_WRITE;
484 op.dest.format = format;
485 op.dest.stride = dst_lev->stride;
486 op.dest.tiling = dst->layout;
488 op.dest.swizzle[x] = x;