Lines Matching refs:op
108 emit_blt_clearimage(struct etna_cmd_stream *stream, const struct blt_clear_op *op)
110 etna_cmd_stream_reserve(stream, 64*2); /* Make sure BLT op doesn't get broken up */
113 assert(op->dest.bpp);
114 etna_set_state(stream, VIVS_BLT_CONFIG, VIVS_BLT_CONFIG_CLEAR_BPP(op->dest.bpp-1));
119 etna_set_state(stream, VIVS_BLT_DEST_STRIDE, blt_compute_stride_bits(&op->dest));
120 etna_set_state(stream, VIVS_BLT_DEST_CONFIG, blt_compute_img_config_bits(&op->dest, true));
121 etna_set_state_reloc(stream, VIVS_BLT_DEST_ADDR, &op->dest.addr);
122 etna_set_state(stream, VIVS_BLT_SRC_STRIDE, blt_compute_stride_bits(&op->dest));
123 etna_set_state(stream, VIVS_BLT_SRC_CONFIG, blt_compute_img_config_bits(&op->dest, false));
124 etna_set_state_reloc(stream, VIVS_BLT_SRC_ADDR, &op->dest.addr);
125 etna_set_state(stream, VIVS_BLT_DEST_POS, VIVS_BLT_DEST_POS_X(op->rect_x) | VIVS_BLT_DEST_POS_Y(op->rect_y));
126 etna_set_state(stream, VIVS_BLT_IMAGE_SIZE, VIVS_BLT_IMAGE_SIZE_WIDTH(op->rect_w) | VIVS_BLT_IMAGE_SIZE_HEIGHT(op->rect_h));
127 etna_set_state(stream, VIVS_BLT_CLEAR_COLOR0, op->clear_value[0]);
128 etna_set_state(stream, VIVS_BLT_CLEAR_COLOR1, op->clear_value[1]);
129 etna_set_state(stream, VIVS_BLT_CLEAR_BITS0, op->clear_bits[0]);
130 etna_set_state(stream, VIVS_BLT_CLEAR_BITS1, op->clear_bits[1]);
131 if (op->dest.use_ts) {
132 etna_set_state_reloc(stream, VIVS_BLT_DEST_TS, &op->dest.ts_addr);
133 etna_set_state_reloc(stream, VIVS_BLT_SRC_TS, &op->dest.ts_addr);
134 etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE0, op->dest.ts_clear_value[0]);
135 etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE1, op->dest.ts_clear_value[1]);
136 etna_set_state(stream, VIVS_BLT_SRC_TS_CLEAR_VALUE0, op->dest.ts_clear_value[0]);
137 etna_set_state(stream, VIVS_BLT_SRC_TS_CLEAR_VALUE1, op->dest.ts_clear_value[1]);
147 emit_blt_copyimage(struct etna_cmd_stream *stream, const struct blt_imgcopy_op *op)
153 VIVS_BLT_CONFIG_SRC_ENDIAN(op->src.endian_mode) |
154 VIVS_BLT_CONFIG_DEST_ENDIAN(op->dest.endian_mode));
155 etna_set_state(stream, VIVS_BLT_SRC_STRIDE, blt_compute_stride_bits(&op->src));
156 etna_set_state(stream, VIVS_BLT_SRC_CONFIG, blt_compute_img_config_bits(&op->src, false));
158 blt_compute_swizzle_bits(&op->src, false) |
159 blt_compute_swizzle_bits(&op->dest, true));
162 if (op->src.use_ts) {
163 etna_set_state_reloc(stream, VIVS_BLT_SRC_TS, &op->src.ts_addr);
164 etna_set_state(stream, VIVS_BLT_SRC_TS_CLEAR_VALUE0, op->src.ts_clear_value[0]);
165 etna_set_state(stream, VIVS_BLT_SRC_TS_CLEAR_VALUE1, op->src.ts_clear_value[1]);
167 etna_set_state_reloc(stream, VIVS_BLT_SRC_ADDR, &op->src.addr);
168 etna_set_state(stream, VIVS_BLT_DEST_STRIDE, blt_compute_stride_bits(&op->dest));
170 blt_compute_img_config_bits(&op->dest, true) |
171 COND(op->flip_y, BLT_IMAGE_CONFIG_FLIP_Y));
172 assert(!op->dest.use_ts); /* Dest TS path doesn't work for copies? */
173 if (op->dest.use_ts) {
174 etna_set_state_reloc(stream, VIVS_BLT_DEST_TS, &op->dest.ts_addr);
175 etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE0, op->dest.ts_clear_value[0]);
176 etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE1, op->dest.ts_clear_value[1]);
178 etna_set_state_reloc(stream, VIVS_BLT_DEST_ADDR, &op->dest.addr);
179 etna_set_state(stream, VIVS_BLT_SRC_POS, VIVS_BLT_DEST_POS_X(op->src_x) | VIVS_BLT_DEST_POS_Y(op->src_y));
180 etna_set_state(stream, VIVS_BLT_DEST_POS, VIVS_BLT_DEST_POS_X(op->dest_x) | VIVS_BLT_DEST_POS_Y(op->dest_y));
181 etna_set_state(stream, VIVS_BLT_IMAGE_SIZE, VIVS_BLT_IMAGE_SIZE_WIDTH(op->rect_w) | VIVS_BLT_IMAGE_SIZE_HEIGHT(op->rect_h));
192 emit_blt_inplace(struct etna_cmd_stream *stream, const struct blt_inplace_op *op)
194 assert(op->bpp > 0 && util_is_power_of_two_nonzero(op->bpp));
198 VIVS_BLT_CONFIG_INPLACE_TS_MODE(op->ts_mode) |
200 (util_logbase2(op->bpp) << VIVS_BLT_CONFIG_INPLACE_BPP__SHIFT));
201 etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE0, op->ts_clear_value[0]);
202 etna_set_state(stream, VIVS_BLT_DEST_TS_CLEAR_VALUE1, op->ts_clear_value[1]);
203 etna_set_state_reloc(stream, VIVS_BLT_DEST_ADDR, &op->addr);
204 etna_set_state_reloc(stream, VIVS_BLT_DEST_TS, &op->ts_addr);
205 etna_set_state(stream, 0x14068, op->num_tiles);
439 struct blt_inplace_op op = {};
441 op.addr.bo = src->bo;
442 op.addr.offset = src_lev->offset + blit_info->src.box.z * src_lev->layer_stride;
443 op.addr.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
444 op.ts_addr.bo = src->ts_bo;
445 op.ts_addr.offset = src_lev->ts_offset + blit_info->src.box.z * src_lev->ts_layer_stride;
446 op.ts_addr.flags = ETNA_RELOC_READ;
447 op.ts_clear_value[0] = src_lev->clear_value;
448 op.ts_clear_value[1] = src_lev->clear_value;
449 op.ts_mode = src_lev->ts_mode;
450 op.num_tiles = DIV_ROUND_UP(src_lev->size,
452 op.bpp = util_format_get_blocksize(src->base.format);
456 emit_blt_inplace(ctx->stream, &op);
458 /* Copy op */
459 struct blt_imgcopy_op op = {};
461 op.src.addr.bo = src->bo;
462 op.src.addr.offset = src_lev->offset + blit_info->src.box.z * src_lev->layer_stride;
463 op.src.addr.flags = ETNA_RELOC_READ;
464 op.src.format = format;
465 op.src.stride = src_lev->stride;
466 op.src.tiling = src->layout;
468 op.src.swizzle[x] = x;
471 op.src.use_ts = 1;
472 op.src.ts_addr.bo = src->ts_bo;
473 op.src.ts_addr.offset = src_lev->ts_offset + blit_info->src.box.z * src_lev->ts_layer_stride;
474 op.src.ts_addr.flags = ETNA_RELOC_READ;
475 op.src.ts_clear_value[0] = src_lev->clear_value;
476 op.src.ts_clear_value[1] = src_lev->clear_value;
477 op.src.ts_mode = src_lev->ts_mode;
478 op.src.ts_compress_fmt = src_lev->ts_compress_fmt;
481 op.dest.addr.bo = dst->bo;
482 op.dest.addr.offset = dst_lev->offset + blit_info->dst.box.z * dst_lev->layer_stride;
483 op.dest.addr.flags = ETNA_RELOC_WRITE;
484 op.dest.format = format;
485 op.dest.stride = dst_lev->stride;
486 op.dest.tiling = dst->layout;
488 op.dest.swizzle[x] = x;
490 op.dest_x = blit_info->dst.box.x;
491 op.dest_y = blit_info->dst.box.y;
492 op.src_x = blit_info->src.box.x;
493 op.src_y = blit_info->src.box.y;
494 op.rect_w = blit_info->dst.box.width;
495 op.rect_h = blit_info->dst.box.height;
498 op.flip_y = 1;
499 op.src_y += blit_info->src.box.height;
502 assert(op.src_x < src_lev->padded_width);
503 assert(op.src_y < src_lev->padded_height);
504 assert((op.src_x + op.rect_w) <= src_lev->padded_width);
505 assert((op.src_y + op.rect_h) <= src_lev->padded_height);
506 assert(op.dest_x < dst_lev->padded_width);
507 assert(op.dest_y < dst_lev->padded_height);
508 assert((op.dest_x + op.rect_w) <= dst_lev->padded_width);
509 assert((op.dest_y + op.rect_h) <= dst_lev->padded_height);
513 emit_blt_copyimage(ctx->stream, &op);