Lines Matching defs:nir
35 #include "nir.h"
36 #include "nir/nir_draw_helpers.h"
37 #include "nir/tgsi_to_nir.h"
38 #include "compiler/nir/nir_builder.h"
94 struct d3d12_shader_key *key, struct nir_shader *nir)
99 shader->nir = nir;
102 NIR_PASS_V(nir, nir_lower_samplers);
103 NIR_PASS_V(nir, dxil_nir_split_typed_samplers);
105 NIR_PASS_V(nir, nir_opt_dce);
108 NIR_PASS_V(nir, nir_remove_dead_variables, nir_var_uniform, &dead_var_opts);
111 NIR_PASS_V(nir, dxil_lower_sample_to_txf_for_integer_tex,
116 dxil_nir_lower_vs_vertex_conversion(nir, key->vs.format_conversion);
118 uint32_t num_ubos_before_lower_to_ubo = nir->info.num_ubos;
119 uint32_t num_uniforms_before_lower_to_ubo = nir->num_uniforms;
120 NIR_PASS_V(nir, nir_lower_uniforms_to_ubo, false, false);
122 nir->info.num_ubos > num_ubos_before_lower_to_ubo;
126 NIR_PASS_V(nir, d3d12_nir_invert_depth, key->invert_depth, key->halfz);
128 NIR_PASS_V(nir, nir_lower_clip_halfz);
129 NIR_PASS_V(nir, d3d12_lower_yflip);
131 NIR_PASS_V(nir, nir_lower_packed_ubo_loads);
132 NIR_PASS_V(nir, d3d12_lower_load_draw_params);
133 NIR_PASS_V(nir, d3d12_lower_load_patch_vertices_in);
134 NIR_PASS_V(nir, d3d12_lower_state_vars, shader);
135 NIR_PASS_V(nir, dxil_nir_lower_bool_input);
136 NIR_PASS_V(nir, dxil_nir_lower_loads_stores_to_dxil);
137 NIR_PASS_V(nir, dxil_nir_lower_atomics_to_dxil);
138 NIR_PASS_V(nir, dxil_nir_lower_double_math);
141 NIR_PASS_V(nir, d3d12_disable_multisampling);
157 if (!nir_to_dxil(nir, &opts, &tmp)) {
164 nir_foreach_variable_with_modes(var, nir, nir_var_uniform) {
176 nir_foreach_image_variable(var, nir) {
186 if(nir->info.num_ubos) {
188 unsigned num_ubo_bindings = nir->info.num_ubos - (shader->state_vars_used ? 1 : 0);
440 mode = (enum pipe_prim_type)last_vertex_stage->current->nir->info.gs.output_primitive;
465 nir_foreach_variable_with_modes(input, fs->current->nir,
508 create_varying_from_info(nir_shader *nir, struct d3d12_varying_info *info,
517 var = nir_variable_create(nir, mode, info->slots[slot].types[slot_frac], tmp);
528 NIR_PASS_V(nir, d3d12_write_0_to_new_varying, var);
534 create_varyings_from_info(nir_shader *nir, struct d3d12_varying_info *info,
539 create_varying_from_info(nir, info, slot, u_bit_scan(&mask), mode, patch);
582 nir_foreach_variable_with_modes(input, fs->current->nir,
886 uint64_t mask = prev->current->nir->info.outputs_written & ~system_out_values;
887 fill_varyings(&key->required_varying_inputs, prev->current->nir,
889 key->prev_varying_outputs = prev->current->nir->info.outputs_written;
892 uint32_t patch_mask = prev->current->nir->info.patch_outputs_written;
893 fill_varyings(&key->ds.required_patch_inputs, prev->current->nir,
910 key->input_clip_size = prev->current->nir->info.clip_distance_array_size;
919 uint64_t mask = next->current->nir->info.inputs_read & ~system_generated_in_values;
920 fill_varyings(&key->required_varying_outputs, next->current->nir,
924 uint32_t patch_mask = next->current->nir->info.patch_outputs_read;
925 fill_varyings(&key->hs.required_patch_outputs, prev->current->nir,
930 key->next_varying_inputs = next->current->nir->info.inputs_read;
980 if (next && next->current->nir->info.stage == MESA_SHADER_TESS_EVAL) {
981 key->hs.primitive_mode = next->current->nir->info.tess._primitive_mode;
982 key->hs.ccw = next->current->nir->info.tess.ccw;
983 key->hs.point_mode = next->current->nir->info.tess.point_mode;
984 key->hs.spacing = next->current->nir->info.tess.spacing;
993 if (prev && prev->current->nir->info.stage == MESA_SHADER_TESS_CTRL)
994 key->ds.tcs_vertices_out = prev->current->nir->info.tess.tcs_vertices_out;
1291 scan_texture_use(nir_shader *nir)
1294 nir_foreach_function(func, nir) {
1347 struct nir_shader *nir,
1351 unsigned tex_scan_result = scan_texture_use(nir);
1354 sel->workgroup_size_variable = nir->info.workgroup_size_variable;
1359 NIR_PASS_V(nir, dxil_nir_lower_int_cubemaps, true);
1362 sel->initial = nir;
1401 struct nir_shader *nir = NULL;
1404 nir = (nir_shader *)shader->ir.nir;
1407 nir = tgsi_to_nir(shader->tokens, ctx->base.screen, false);
1410 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
1412 update_so_info(&sel->so_info, nir->info.outputs_written);
1414 assert(nir != NULL);
1418 NIR_PASS_V(nir, dxil_nir_split_clip_cull_distance);
1419 NIR_PASS_V(nir, d3d12_split_multistream_varyings);
1421 if (nir->info.stage != MESA_SHADER_VERTEX)
1422 nir->info.inputs_read =
1423 dxil_reassign_driver_locations(nir, nir_var_shader_in,
1424 prev ? prev->current->nir->info.outputs_written : 0);
1426 nir->info.inputs_read = dxil_sort_by_driver_location(nir, nir_var_shader_in);
1428 if (nir->info.stage != MESA_SHADER_FRAGMENT) {
1429 nir->info.outputs_written =
1430 dxil_reassign_driver_locations(nir, nir_var_shader_out,
1431 next ? next->current->nir->info.inputs_read : 0);
1433 NIR_PASS_V(nir, nir_lower_fragcoord_wtrans);
1434 NIR_PASS_V(nir, d3d12_lower_sample_pos);
1435 dxil_sort_ps_outputs(nir);
1438 return d3d12_create_shader_impl(ctx, sel, nir, prev, next);
1448 struct nir_shader *nir = NULL;
1451 nir = (nir_shader *)shader->prog;
1454 nir = tgsi_to_nir(shader->prog, ctx->base.screen, false);
1457 nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
1459 NIR_PASS_V(nir, d3d12_lower_compute_state_vars);
1461 return d3d12_create_shader_impl(ctx, sel, nir, nullptr, nullptr);