Lines Matching defs:info
118 uint32_t num_ubos_before_lower_to_ubo = nir->info.num_ubos;
122 nir->info.num_ubos > num_ubos_before_lower_to_ubo;
186 if(nir->info.num_ubos) {
188 unsigned num_ubo_bindings = nir->info.num_ubos - (shader->state_vars_used ? 1 : 0);
299 if (fs->initial->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_COLOR))
332 return fs && fs->initial->info.inputs_read & VARYING_BIT_POS;
360 (vs->initial->info.outputs_written & VARYING_BIT_EDGE ||
373 unsigned mask = ctx->gfx_stages[PIPE_SHADER_GEOMETRY]->initial->info.gs.active_stream_mask & ~1;
391 return (gs->initial->info.gs.output_primitive == GL_POINTS &&
392 (gs->initial->info.outputs_written & VARYING_BIT_PSIZ ||
394 (gs->initial->info.gs.active_stream_mask == 1 ||
403 vs->initial->info.outputs_written & VARYING_BIT_PSIZ)) &&
404 (vs->initial->info.outputs_written & VARYING_BIT_POS));
440 mode = (enum pipe_prim_type)last_vertex_stage->current->nir->info.gs.output_primitive;
453 gs->initial->info.gs.vertices_out > u_prim_vertex_count(mode)->min);
508 create_varying_from_info(nir_shader *nir, struct d3d12_varying_info *info,
516 info->slots[slot].vars[slot_frac].driver_location);
517 var = nir_variable_create(nir, mode, info->slots[slot].types[slot_frac], tmp);
520 var->data.driver_location = info->slots[slot].vars[slot_frac].driver_location;
521 var->data.interpolation = info->slots[slot].vars[slot_frac].interpolation;
522 var->data.patch = info->slots[slot].patch;
523 var->data.compact = info->slots[slot].vars[slot_frac].compact;
534 create_varyings_from_info(nir_shader *nir, struct d3d12_varying_info *info,
537 unsigned mask = info->slots[slot].location_frac_mask;
539 create_varying_from_info(nir, info, slot, u_bit_scan(&mask), mode, patch);
543 fill_varyings(struct d3d12_varying_info *info, nir_shader *s,
559 if ((s->info.stage == MESA_SHADER_GEOMETRY ||
560 s->info.stage == MESA_SHADER_TESS_CTRL) &&
564 info->slots[slot].types[var->data.location_frac] = type;
566 info->slots[slot].patch = var->data.patch;
567 auto& var_slot = info->slots[slot].vars[var->data.location_frac];
571 info->mask |= slot_bit;
572 info->slots[slot].location_frac_mask |= (1 << var->data.location_frac);
608 key.has_front_face = BITSET_TEST(fs->initial->info.system_values_read, SYSTEM_VALUE_FRONT_FACE);
628 vs->initial->info.outputs_written, false);
658 vs->initial->info.outputs_written, false);
886 uint64_t mask = prev->current->nir->info.outputs_written & ~system_out_values;
889 key->prev_varying_outputs = prev->current->nir->info.outputs_written;
892 uint32_t patch_mask = prev->current->nir->info.patch_outputs_written;
905 /* Get the input clip distance size. The info's clip_distance_array_size corresponds
910 key->input_clip_size = prev->current->nir->info.clip_distance_array_size;
919 uint64_t mask = next->current->nir->info.inputs_read & ~system_generated_in_values;
924 uint32_t patch_mask = next->current->nir->info.patch_outputs_read;
930 key->next_varying_inputs = next->current->nir->info.inputs_read;
963 if (sel->is_variant && next && next->initial->info.inputs_read & VARYING_BIT_PRIMITIVE_ID)
980 if (next && next->current->nir->info.stage == MESA_SHADER_TESS_EVAL) {
981 key->hs.primitive_mode = next->current->nir->info.tess._primitive_mode;
982 key->hs.ccw = next->current->nir->info.tess.ccw;
983 key->hs.point_mode = next->current->nir->info.tess.point_mode;
984 key->hs.spacing = next->current->nir->info.tess.spacing;
993 if (prev && prev->current->nir->info.stage == MESA_SHADER_TESS_CTRL)
994 key->ds.tcs_vertices_out = prev->current->nir->info.tess.tcs_vertices_out;
1151 new_nir_variant->info.workgroup_size[0] = key.cs.workgroup_size[0];
1152 new_nir_variant->info.workgroup_size[1] = key.cs.workgroup_size[1];
1153 new_nir_variant->info.workgroup_size[2] = key.cs.workgroup_size[2];
1156 if (new_nir_variant->info.stage == MESA_SHADER_TESS_CTRL) {
1157 new_nir_variant->info.tess._primitive_mode = (tess_primitive_mode)key.hs.primitive_mode;
1158 new_nir_variant->info.tess.ccw = key.hs.ccw;
1159 new_nir_variant->info.tess.point_mode = key.hs.point_mode;
1160 new_nir_variant->info.tess.spacing = key.hs.spacing;
1163 } else if (new_nir_variant->info.stage == MESA_SHADER_TESS_EVAL) {
1164 new_nir_variant->info.tess.tcs_vertices_out = key.ds.tcs_vertices_out;
1183 uint64_t mask = key.required_varying_inputs.mask & ~new_nir_variant->info.inputs_read;
1184 new_nir_variant->info.inputs_read |= mask;
1191 uint32_t patch_mask = (uint32_t)key.ds.required_patch_inputs.mask & ~new_nir_variant->info.patch_inputs_read;
1192 new_nir_variant->info.patch_inputs_read |= patch_mask;
1204 uint64_t mask = key.required_varying_outputs.mask & ~new_nir_variant->info.outputs_written;
1205 new_nir_variant->info.outputs_written |= mask;
1212 uint32_t patch_mask = (uint32_t)key.hs.required_patch_outputs.mask & ~new_nir_variant->info.patch_outputs_written;
1213 new_nir_variant->info.patch_outputs_written |= patch_mask;
1354 sel->workgroup_size_variable = nir->info.workgroup_size_variable;
1412 update_so_info(&sel->so_info, nir->info.outputs_written);
1421 if (nir->info.stage != MESA_SHADER_VERTEX)
1422 nir->info.inputs_read =
1424 prev ? prev->current->nir->info.outputs_written : 0);
1426 nir->info.inputs_read = dxil_sort_by_driver_location(nir, nir_var_shader_in);
1428 if (nir->info.stage != MESA_SHADER_FRAGMENT) {
1429 nir->info.outputs_written =
1431 next ? next->current->nir->info.inputs_read : 0);
1503 const struct pipe_grid_info *info)
1506 return info->block;
1511 d3d12_select_compute_shader_variants(struct d3d12_context *ctx, const struct pipe_grid_info *info)
1516 sel_ctx.variable_workgroup_size = workgroup_size_variable(ctx, info);