Lines Matching refs:lrm
577 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
578 lrm.RegisterAddress = reg;
579 lrm.MemoryAddress = ro_bo(bo, offset);
7952 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
7953 lrm.RegisterAddress = _3DPRIM_VERTEX_COUNT;
7954 lrm.MemoryAddress = ro_bo(bo, indirect->offset + 0);
7956 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
7957 lrm.RegisterAddress = _3DPRIM_INSTANCE_COUNT;
7958 lrm.MemoryAddress = ro_bo(bo, indirect->offset + 4);
7960 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
7961 lrm.RegisterAddress = _3DPRIM_START_VERTEX;
7962 lrm.MemoryAddress = ro_bo(bo, indirect->offset + 8);
7965 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
7966 lrm.RegisterAddress = _3DPRIM_BASE_VERTEX;
7967 lrm.MemoryAddress = ro_bo(bo, indirect->offset + 12);
7969 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
7970 lrm.RegisterAddress = _3DPRIM_START_INSTANCE;
7971 lrm.MemoryAddress = ro_bo(bo, indirect->offset + 16);
7974 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
7975 lrm.RegisterAddress = _3DPRIM_START_INSTANCE;
7976 lrm.MemoryAddress = ro_bo(bo, indirect->offset + 12);
8194 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
8195 lrm.RegisterAddress = GPGPU_DISPATCHDIMX;
8196 lrm.MemoryAddress = ro_bo(bo, grid_size->offset + 0);
8198 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
8199 lrm.RegisterAddress = GPGPU_DISPATCHDIMY;
8200 lrm.MemoryAddress = ro_bo(bo, grid_size->offset + 4);
8202 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
8203 lrm.RegisterAddress = GPGPU_DISPATCHDIMZ;
8204 lrm.MemoryAddress = ro_bo(bo, grid_size->offset + 8);