Lines Matching defs:reg
492 crocus_store_register_mem32(struct crocus_batch *batch, uint32_t reg,
497 srm.RegisterAddress = reg;
509 crocus_store_register_mem64(struct crocus_batch *batch, uint32_t reg,
513 crocus_store_register_mem32(batch, reg + 0, bo, offset + 0, predicated);
514 crocus_store_register_mem32(batch, reg + 4, bo, offset + 4, predicated);
520 _crocus_emit_lri(struct crocus_batch *batch, uint32_t reg, uint32_t val)
523 lri.RegisterOffset = reg;
556 crocus_load_register_imm32(struct crocus_batch *batch, uint32_t reg,
559 _crocus_emit_lri(batch, reg, val);
563 crocus_load_register_imm64(struct crocus_batch *batch, uint32_t reg,
566 _crocus_emit_lri(batch, reg + 0, val & 0xffffffff);
567 _crocus_emit_lri(batch, reg + 4, val >> 32);
574 crocus_load_register_mem32(struct crocus_batch *batch, uint32_t reg,
578 lrm.RegisterAddress = reg;
588 crocus_load_register_mem64(struct crocus_batch *batch, uint32_t reg,
591 crocus_load_register_mem32(batch, reg + 0, bo, offset + 0);
592 crocus_load_register_mem32(batch, reg + 4, bo, offset + 4);
885 GLuint reg = 0;
889 reg = 0;
890 ice->curbe.wm_start = reg;
891 ice->curbe.wm_size = nr_fp_regs; reg += nr_fp_regs;
892 ice->curbe.clip_start = reg;
893 ice->curbe.clip_size = nr_clip_regs; reg += nr_clip_regs;
894 ice->curbe.vs_start = reg;
895 ice->curbe.vs_size = nr_vp_regs; reg += nr_vp_regs;
896 ice->curbe.total_size = reg;
1115 crocus_emit_reg(batch, GENX(L3CNTLREG), reg) {
1116 reg.SLMEnable = cfg->n[INTEL_L3P_SLM] > 0;
1117 reg.URBAllocation = cfg->n[INTEL_L3P_URB];
1118 reg.ROAllocation = cfg->n[INTEL_L3P_RO];
1119 reg.DCAllocation = cfg->n[INTEL_L3P_DC];
1120 reg.AllAllocation = cfg->n[INTEL_L3P_ALL];
1139 crocus_pack_state(GENX(L3SQCREG1), &l3sqcr1, reg) {
1140 reg.ConvertDC_UC = !has_dc;
1141 reg.ConvertIS_UC = !has_is;
1142 reg.ConvertC_UC = !has_c;
1143 reg.ConvertT_UC = !has_t;
1145 reg.L3SQGeneralPriorityCreditInitialization = SQGPCI_DEFAULT;
1147 reg.L3SQGeneralPriorityCreditInitialization =
1150 reg.L3SQHighPriorityCreditInitialization = SQHPCI_DEFAULT;
1153 crocus_pack_state(GENX(L3CNTLREG2), &l3cr2, reg) {
1154 reg.SLMEnable = has_slm;
1155 reg.URBLowBandwidth = urb_low_bw;
1156 reg.URBAllocation = cfg->n[INTEL_L3P_URB] - n0_urb;
1158 reg.ALLAllocation = cfg->n[INTEL_L3P_ALL];
1160 reg.ROAllocation = cfg->n[INTEL_L3P_RO];
1161 reg.DCAllocation = cfg->n[INTEL_L3P_DC];
1164 crocus_pack_state(GENX(L3CNTLREG3), &l3cr3, reg) {
1165 reg.ISAllocation = cfg->n[INTEL_L3P_IS];
1166 reg.ISLowBandwidth = 0;
1167 reg.CAllocation = cfg->n[INTEL_L3P_C];
1168 reg.CLowBandwidth = 0;
1169 reg.TAllocation = cfg->n[INTEL_L3P_T];
1170 reg.TLowBandwidth = 0;
1181 crocus_pack_state(GENX(SCRATCH1), &scratch1, reg) {
1182 reg.L3AtomicDisable = !has_dc;
1184 crocus_pack_state(GENX(CHICKEN3), &chicken3, reg) {
1185 reg.L3AtomicDisableMask = true;
1186 reg.L3AtomicDisable = !has_dc;
1377 crocus_emit_reg(batch, GENX(INSTPM), reg) {
1378 reg.CONSTANT_BUFFERAddressOffsetDisable = true;
1379 reg.CONSTANT_BUFFERAddressOffsetDisableMask = true;
1942 crocus_emit_reg(batch, GENX(CACHE_MODE_1), reg) {
1943 reg.NPPMAFixEnable = enable;
1944 reg.NPEarlyZFailsDisable = enable;
1945 reg.NPPMAFixEnableMask = true;
1946 reg.NPEarlyZFailsDisableMask = true;