Lines Matching defs:flush
378 /* Need to flush before changing clip max threads for errata. */
422 * We make this an end-of-pipe sync instead of a normal flush because we
475 * experimentation, shows that flush the texture cache appears to be
1080 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1090 * stalling flush as the hardware documentation suggests, because that
1106 /* Now send a third stalling flush to make sure that invalidation is
1951 * The render cache flush is also necessary if stencil writes are enabled.
4072 batch->ice->ctx.flush(&batch->ice->ctx, &out_fence, 0);
4154 uint32_t flush = 0;
4161 flush |= crocus_flush_bits_for_history(res);
4166 "make streamout results visible", flush);
5740 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
6533 * cause an in most cases useless DC flush when the lowermost stage with
6832 * "Note: Because of corruption in IVB:GT2, software needs to flush the
6836 * The hardware architects have clarified that in this context "flush the
8624 * cache invalidation bit set, program a PIPECONTROL flush command
8966 * doesn't exist on Gen6). So for now we just do a full pipeline flush as