Lines Matching defs:batch
59 * we can simply memcpy them into a batch buffer.
70 * the context state and emit the commands into the actual batch.
328 stream_state(struct crocus_batch *batch,
333 uint32_t offset = ALIGN(batch->state.used, alignment);
335 if (offset + size >= STATE_SZ && !batch->no_wrap) {
336 crocus_batch_flush(batch);
337 offset = ALIGN(batch->state.used, alignment);
338 } else if (offset + size >= batch->state.bo->size) {
340 MIN2(batch->state.bo->size + batch->state.bo->size / 2,
342 crocus_grow_buffer(batch, true, batch->state.used, new_size);
343 assert(offset + size < batch->state.bo->size);
346 crocus_record_state_size(batch->state_sizes, offset, size);
348 batch->state.used = offset + size;
351 return (uint32_t *)batch->state.map + (offset >> 2);
358 emit_state(struct crocus_batch *batch, const void *data, unsigned size,
362 uint32_t *map = stream_state(batch, size, alignment, &offset);
372 upload_pipelined_state_pointers(struct crocus_batch *batch,
379 crocus_emit_cmd(batch, GENX(MI_FLUSH), foo);
382 crocus_emit_cmd(batch, GENX(3DSTATE_PIPELINED_POINTERS), pp) {
383 pp.PointertoVSState = ro_bo(batch->state.bo, vs_offset);
386 pp.PointertoGSState = ro_bo(batch->state.bo, gs_offset);
388 pp.PointertoCLIPState = ro_bo(batch->state.bo, clip_offset);
389 pp.PointertoSFState = ro_bo(batch->state.bo, sf_offset);
390 pp.PointertoWMState = ro_bo(batch->state.bo, wm_offset);
391 pp.PointertoColorCalcState = ro_bo(batch->state.bo, cc_offset);
406 flush_before_state_base_change(struct crocus_batch *batch)
418 * and flushes prior to executing our batch. However, it doesn't seem
432 crocus_emit_end_of_pipe_sync(batch,
441 flush_after_state_base_change(struct crocus_batch *batch)
481 crocus_emit_end_of_pipe_sync(batch,
492 crocus_store_register_mem32(struct crocus_batch *batch, uint32_t reg,
496 crocus_emit_cmd(batch, GENX(MI_STORE_REGISTER_MEM), srm) {
509 crocus_store_register_mem64(struct crocus_batch *batch, uint32_t reg,
513 crocus_store_register_mem32(batch, reg + 0, bo, offset + 0, predicated);
514 crocus_store_register_mem32(batch, reg + 4, bo, offset + 4, predicated);
520 _crocus_emit_lri(struct crocus_batch *batch, uint32_t reg, uint32_t val)
522 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
531 _crocus_emit_lrr(struct crocus_batch *batch, uint32_t dst, uint32_t src)
533 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_REG), lrr) {
540 crocus_load_register_reg32(struct crocus_batch *batch, uint32_t dst,
543 _crocus_emit_lrr(batch, dst, src);
547 crocus_load_register_reg64(struct crocus_batch *batch, uint32_t dst,
550 _crocus_emit_lrr(batch, dst, src);
551 _crocus_emit_lrr(batch, dst + 4, src + 4);
556 crocus_load_register_imm32(struct crocus_batch *batch, uint32_t reg,
559 _crocus_emit_lri(batch, reg, val);
563 crocus_load_register_imm64(struct crocus_batch *batch, uint32_t reg,
566 _crocus_emit_lri(batch, reg + 0, val & 0xffffffff);
567 _crocus_emit_lri(batch, reg + 4, val >> 32);
574 crocus_load_register_mem32(struct crocus_batch *batch, uint32_t reg,
577 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
588 crocus_load_register_mem64(struct crocus_batch *batch, uint32_t reg,
591 crocus_load_register_mem32(batch, reg + 0, bo, offset + 0);
592 crocus_load_register_mem32(batch, reg + 4, bo, offset + 4);
597 crocus_store_data_imm32(struct crocus_batch *batch,
601 crocus_emit_cmd(batch, GENX(MI_STORE_DATA_IMM), sdi) {
610 crocus_store_data_imm64(struct crocus_batch *batch,
617 void *map = crocus_get_command_space(batch, 4 * 5);
618 _crocus_pack_command(batch, GENX(MI_STORE_DATA_IMM), map, sdi) {
629 crocus_copy_mem_mem(struct crocus_batch *batch,
640 crocus_load_register_mem32(batch, CROCUS_TEMP_REG,
642 crocus_store_register_mem32(batch, CROCUS_TEMP_REG,
700 crocus_calculate_urb_fence(struct crocus_batch *batch, unsigned csize,
703 struct crocus_context *ice = batch->ice;
795 crocus_upload_urb_fence(struct crocus_batch *batch)
798 _crocus_pack_command(batch, GENX(URB_FENCE), urb_fence, urb) {
806 urb.VSFence = batch->ice->urb.gs_start;
807 urb.GSFence = batch->ice->urb.clip_start;
808 urb.CLIPFence = batch->ice->urb.sf_start;
809 urb.SFFence = batch->ice->urb.cs_start;
810 urb.CSFence = batch->ice->urb.size;
814 if ((crocus_batch_bytes_used(batch) & 15) > 12) {
815 int pad = 16 - (crocus_batch_bytes_used(batch) & 15);
817 *(uint32_t *)batch->command.map_next = 0;
818 batch->command.map_next += sizeof(uint32_t);
822 crocus_batch_emit(batch, urb_fence, sizeof(uint32_t) * 3);
826 calculate_curbe_offsets(struct crocus_batch *batch)
828 struct crocus_context *ice = batch->ice;
964 gen4_upload_curbe(struct crocus_batch *batch)
966 struct crocus_context *ice = batch->ice;
1021 crocus_emit_cmd(batch, GENX(CONSTANT_BUFFER), cb) {
1051 crocus_emit_cmd(batch, GENX(3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP), clamp);
1064 setup_l3_config(struct crocus_batch *batch, const struct intel_l3_config *cfg)
1067 const struct intel_device_info *devinfo = &batch->screen->devinfo;
1082 crocus_emit_pipe_control_flush(batch, "l3_config",
1100 crocus_emit_pipe_control_flush(batch, "l3 config",
1109 crocus_emit_pipe_control_flush(batch, "l3 config",
1115 crocus_emit_reg(batch, GENX(L3CNTLREG), reg) {
1174 crocus_emit_lri(batch, L3SQCREG1, l3sqcr1);
1175 crocus_emit_lri(batch, L3CNTLREG2, l3cr2);
1176 crocus_emit_lri(batch, L3CNTLREG3, l3cr3);
1188 crocus_emit_lri(batch, SCRATCH1, scratch1);
1189 crocus_emit_lri(batch, CHICKEN3, chicken3);
1195 emit_l3_state(struct crocus_batch *batch, bool compute)
1198 compute ? batch->screen->l3_config_cs : batch->screen->l3_config_3d;
1200 setup_l3_config(batch, cfg);
1210 gen7_emit_cs_stall_flush(struct crocus_batch *batch)
1212 crocus_emit_pipe_control_write(batch,
1216 batch->ice->workaround_bo,
1217 batch->ice->workaround_offset, 0);
1222 emit_pipeline_select(struct crocus_batch *batch, uint32_t pipeline)
1235 crocus_emit_cmd(batch, GENX(3DSTATE_CC_STATE_POINTERS), t);
1251 crocus_emit_pipe_control_flush(batch,
1258 crocus_emit_pipe_control_flush(batch,
1273 crocus_emit_cmd(batch, GENX(MI_FLUSH), foo);
1276 crocus_emit_cmd(batch, GENX(PIPELINE_SELECT), sel) {
1282 gen7_emit_cs_stall_flush(batch);
1284 crocus_emit_cmd(batch, GENX(3DPRIMITIVE), prim) {
1323 crocus_alloc_push_constants(struct crocus_batch *batch)
1326 batch->screen->devinfo.max_constant_urb_size_kb;
1339 crocus_emit_cmd(batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS), alloc) {
1353 if (batch->screen->devinfo.platform == INTEL_PLATFORM_IVB)
1354 gen7_emit_cs_stall_flush(batch);
1365 crocus_init_render_context(struct crocus_batch *batch)
1367 UNUSED const struct intel_device_info *devinfo = &batch->screen->devinfo;
1369 emit_pipeline_select(batch, _3D);
1371 crocus_emit_cmd(batch, GENX(STATE_SIP), foo);
1374 emit_l3_state(batch, false);
1377 crocus_emit_reg(batch, GENX(INSTPM), reg) {
1384 crocus_emit_cmd(batch, GENX(3DSTATE_AA_LINE_PARAMETERS), foo);
1389 crocus_emit_cmd(batch, GENX(3DSTATE_POLY_STIPPLE_OFFSET), foo);
1392 crocus_alloc_push_constants(batch);
1397 crocus_emit_cmd(batch, GENX(3DSTATE_SAMPLE_PATTERN), pat) {
1405 crocus_emit_cmd(batch, GENX(3DSTATE_WM_CHROMAKEY), foo);
1408 crocus_emit_cmd(batch, GENX(3DSTATE_WM_HZ_OP), foo);
1414 crocus_init_compute_context(struct crocus_batch *batch)
1416 UNUSED const struct intel_device_info *devinfo = &batch->screen->devinfo;
1418 emit_pipeline_select(batch, GPGPU);
1421 emit_l3_state(batch, true);
1521 set_blend_entry_bits(struct crocus_batch *batch, BLEND_ENTRY_GENXML *entry,
1525 struct crocus_context *ice = batch->ice;
1918 struct crocus_batch *batch,
1937 crocus_emit_pipe_control_flush(batch, "PMA fix change (1/2)",
1942 crocus_emit_reg(batch, GENX(CACHE_MODE_1), reg) {
1956 crocus_emit_pipe_control_flush(batch, "PMA fix change (1/2)",
2340 crocus_upload_sampler_state(struct crocus_batch *batch,
2372 _crocus_pack_state(batch, GENX(SAMPLER_STATE), map, samp) {
2434 ro_bo(batch->state.bo, border_color_offset);
2442 crocus_upload_border_color(struct crocus_batch *batch,
2479 uint32_t *sbc = stream_state(batch, sbc_size, sbc_align, bc_offset);
2586 GENX(SAMPLER_BORDER_COLOR_STATE_pack)(batch, sbc, &state);
2597 struct crocus_batch *batch, gl_shader_stage stage)
2615 uint32_t *map = stream_state(batch, size, 32, &shs->sampler_offset);
2629 crocus_upload_border_color(batch, state, tex, &border_color_offset);
2659 crocus_upload_sampler_state(batch, state, border_color_offset, wa, first_level, map);
4065 aggregate_stream_counter(struct crocus_batch *batch, struct crocus_stream_output_target *tgt,
4070 if (crocus_batch_references(batch, tgt->offset_res->bo)) {
4072 batch->ice->ctx.flush(&batch->ice->ctx, &out_fence, 0);
4073 batch->screen->base.fence_finish(&batch->screen->base, &batch->ice->ctx, out_fence, UINT64_MAX);
4074 batch->screen->base.fence_reference(&batch->screen->base, &out_fence, NULL);
4084 crocus_stream_store_prims_written(struct crocus_batch *batch,
4088 u_upload_alloc(batch->ice->ctx.stream_uploader, 0, 4096, 4,
4096 aggregate_stream_counter(batch, tgt, &tgt->prev_count);
4097 aggregate_stream_counter(batch, tgt, &tgt->count);
4100 crocus_emit_mi_flush(batch);
4101 crocus_store_register_mem64(batch, GEN6_SO_NUM_PRIMS_WRITTEN,
4133 struct crocus_batch *batch = &ice->batches[CROCUS_BATCH_RENDER];
4201 crocus_stream_store_prims_written(batch, tgt);
4209 crocus_stream_store_prims_written(batch, tgt);
4232 crocus_load_register_imm32(batch, GEN7_SO_WRITE_OFFSET(i), 0);
4235 crocus_load_register_mem32(batch, GEN7_SO_WRITE_OFFSET(i),
4242 crocus_store_register_mem32(batch, GEN7_SO_WRITE_OFFSET(i),
4403 struct crocus_batch *batch = &ice->batches[CROCUS_BATCH_RENDER];
4413 crocus_emit_cmd(batch, GENX(3DSTATE_GS_SVB_INDEX), svbi) {
4423 crocus_emit_cmd(batch, GENX(3DSTATE_GS_SVB_INDEX), svbi) {
4635 crocus_emit_sbe(struct crocus_batch *batch, const struct crocus_context *ice)
4650 crocus_emit_cmd(batch, GENX(3DSTATE_SBE), sbe) {
4670 crocus_emit_cmd(batch, GENX(3DSTATE_SBE_SWIZ), sbes) {
4917 emit_sized_null_surface(struct crocus_batch *batch,
4923 struct isl_device *isl_dev = &batch->screen->isl_dev;
4924 uint32_t *surf = stream_state(batch, isl_dev->ss.size,
4934 emit_null_surface(struct crocus_batch *batch,
4937 emit_sized_null_surface(batch, 1, 1, 1, 0, 0, out_offset);
4941 emit_null_fb_surface(struct crocus_batch *batch,
4948 emit_null_surface(batch, out_offset);
4965 emit_sized_null_surface(batch, width, height,
4971 emit_surface_state(struct crocus_batch *batch,
4983 struct isl_device *isl_dev = &batch->screen->isl_dev;
5029 .address = crocus_state_reloc(batch,
5058 *aux_addr = crocus_state_reloc(batch,
5064 *aux_addr = crocus_state_reloc(batch,
5074 emit_surface(struct crocus_batch *batch,
5080 struct isl_device *isl_dev = &batch->screen->isl_dev;
5093 uint32_t *surf_state = stream_state(batch, isl_dev->ss.size, isl_dev->ss.align, &offset);
5095 emit_surface_state(batch, res, &surf->surf, adjust_surf, view, true,
5103 emit_rt_surface(struct crocus_batch *batch,
5107 struct isl_device *isl_dev = &batch->screen->isl_dev;
5111 uint32_t *surf_state = stream_state(batch, isl_dev->ss.size, isl_dev->ss.align, &offset);
5113 emit_surface_state(batch, res, &surf->surf, true, view, false,
5121 struct crocus_batch *batch)
5123 UNUSED struct isl_device *isl_dev = &batch->screen->isl_dev;
5126 uint32_t *surf_state = stream_state(batch, isl_dev->ss.size,
5129 .address = crocus_state_reloc(batch, offset + isl_dev->ss.addr_offset,
5142 struct crocus_batch *batch,
5145 UNUSED struct isl_device *isl_dev = &batch->screen->isl_dev;
5148 uint32_t *surf_state = stream_state(batch, isl_dev->ss.size,
5151 .address = crocus_state_reloc(batch, offset + isl_dev->ss.addr_offset,
5166 struct crocus_batch *batch,
5169 UNUSED struct isl_device *isl_dev = &batch->screen->isl_dev;
5175 uint32_t *surf_state = stream_state(batch, isl_dev->ss.size,
5178 .address = crocus_state_reloc(batch, offset + isl_dev->ss.addr_offset,
5193 struct crocus_batch *batch,
5197 UNUSED struct isl_device *isl_dev = &batch->screen->isl_dev;
5200 uint32_t *surf_state = stream_state(batch, isl_dev->ss.size,
5210 .address = crocus_state_reloc(batch, offset + isl_dev->ss.addr_offset,
5223 emit_surface_state(batch, isv->res, &isv->res->surf, false,
5233 struct crocus_batch *batch,
5236 UNUSED struct isl_device *isl_dev = &batch->screen->isl_dev;
5240 uint32_t *surf_state = stream_state(batch, isl_dev->ss.size,
5251 .address = crocus_state_reloc(batch, offset + isl_dev->ss.addr_offset,
5263 .address = crocus_state_reloc(batch, offset + isl_dev->ss.addr_offset,
5275 emit_surface_state(batch, res,
5287 emit_sol_surface(struct crocus_batch *batch,
5291 struct crocus_context *ice = batch->ice;
5348 UNUSED struct isl_device *isl_dev = &batch->screen->isl_dev;
5351 uint32_t *surf_state = stream_state(batch, isl_dev->ss.size,
5354 .address = crocus_state_reloc(batch, offset + isl_dev->ss.addr_offset,
5372 struct crocus_batch *batch,
5408 surf_offsets[s] = emit_surface(batch,
5414 emit_null_fb_surface(batch, ice, &surf_offsets[s]);
5419 emit_null_fb_surface(batch, ice, &surf_offsets[s]);
5426 surf_offsets[s++] = emit_rt_surface(batch,
5435 surf_offsets[s] = emit_grid(ice, batch);
5449 surf_offsets[s] = emit_sol_surface(batch, so_info, i);
5458 surf_offsets[s] = emit_sampler_view(ice, batch, false, view);
5460 emit_null_surface(batch, &surf_offsets[s]);
5469 surf_offsets[s] = emit_sampler_view(ice, batch, true, view);
5471 emit_null_surface(batch, &surf_offsets[s]);
5480 surf_offsets[s] = emit_image_view(ice, batch, view);
5482 emit_null_surface(batch, &surf_offsets[s]);
5487 surf_offsets[s] = emit_ubo_buffer(ice, batch, &shs->constbufs[i]);
5489 emit_null_surface(batch, &surf_offsets[s]);
5494 surf_offsets[s] = emit_ssbo_buffer(ice, batch, &shs->ssbo[i],
5497 emit_null_surface(batch, &surf_offsets[s]);
5505 struct crocus_batch *batch,
5512 return emit_state(batch, table, size, 32);
5520 crocus_update_surface_base_address(struct crocus_batch *batch)
5522 if (batch->state_base_address_emitted)
5525 UNUSED uint32_t mocs = batch->screen->isl_dev.mocs.internal;
5527 flush_before_state_base_change(batch);
5529 crocus_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) {
5535 sba.DynamicStateBaseAddress = ro_bo(batch->state.bo, 0);
5539 sba.SurfaceStateBaseAddress = ro_bo(batch->state.bo, 0);
5545 sba.InstructionBaseAddress = ro_bo(batch->ice->shaders.cache_bo, 0); // TODO!
5594 flush_after_state_base_change(batch);
5613 * batch time), except in the case of the program cache BO
5618 batch->ice->state.dirty |= CROCUS_DIRTY_GEN5_PIPELINED_POINTERS | CROCUS_DIRTY_GEN5_BINDING_TABLE_POINTERS;
5620 batch->ice->state.dirty |= CROCUS_DIRTY_GEN5_BINDING_TABLE_POINTERS | CROCUS_DIRTY_GEN6_SAMPLER_STATE_POINTERS;
5622 batch->state_base_address_emitted = true;
5649 struct crocus_batch *batch,
5684 : ro_bo(batch->ice->workaround_bo,
5685 batch->ice->workaround_offset);
5701 gen7_emit_vs_workaround_flush(struct crocus_batch *batch)
5703 crocus_emit_pipe_control_write(batch,
5707 batch->ice->workaround_bo,
5708 batch->ice->workaround_offset, 0);
5714 struct crocus_batch *batch,
5720 UNUSED uint32_t mocs = crocus_mocs(NULL, &batch->screen->isl_dev);
5724 if (batch->screen->devinfo.platform == INTEL_PLATFORM_IVB)
5725 gen7_emit_vs_workaround_flush(batch);
5728 crocus_emit_cmd(batch, GENX(3DSTATE_CONSTANT_VS), pkt) {
5816 emit_vertex_buffer_state(struct crocus_batch *batch,
5826 _crocus_pack_state(batch, GENX(VERTEX_BUFFER_STATE), *map, vb) {
5837 vb.MOCS = crocus_mocs(bo, &batch->screen->isl_dev);
5866 struct crocus_batch *batch,
5877 crocus_emit_cmd(batch, GENX(3DSTATE_VF_STATISTICS), vf) {
5885 bool ret = calculate_curbe_offsets(batch);
5894 bool ret = crocus_calculate_urb_fence(batch, ice->curbe.total_size,
5909 stream_state(batch,
5931 crocus_emit_cmd(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), ptr) {
5935 crocus_emit_cmd(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS), vp) {
5950 stream_state(batch,
5955 stream_state(batch,
5959 stream_state(batch,
6028 crocus_emit_cmd(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), ptr) {
6032 crocus_emit_cmd(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS), vp) {
6057 genX(crocus_upload_urb)(batch, vs_size, gs_present, gs_size);
6060 const struct intel_device_info *devinfo = &batch->screen->devinfo;
6101 batch->screen->l3_config_3d,
6109 gen7_emit_vs_workaround_flush(batch);
6112 crocus_emit_cmd(batch, GENX(3DSTATE_URB_VS), urb) {
6136 stream_state(batch,
6164 be.IndependentAlphaBlendEnable = set_blend_entry_bits(batch, &entry, cso_blend, i) ||
6192 crocus_emit_cmd(batch, GENX(3DSTATE_CC_STATE_POINTERS), ptr) {
6197 crocus_emit_cmd(batch, GENX(3DSTATE_BLEND_STATE_POINTERS), ptr) {
6213 stream_state(batch,
6219 _crocus_pack_state(batch, GENX(COLOR_CALC_STATE), cc_map, cc) {
6235 cc.IndependentAlphaBlendEnable = set_blend_entry_bits(batch, &cc, cso_blend, 0);
6242 cc.CCViewportStatePointer = ro_bo(batch->state.bo, ice->state.cc_vp_address);
6257 crocus_emit_cmd(batch, GENX(3DSTATE_CC_STATE_POINTERS), ptr) {
6267 crocus_emit_cmd(batch, GENX(3DSTATE_CONSTANT_COLOR), blend_cc) {
6293 setup_constant_buffers(ice, batch, stage, &push_bos);
6295 emit_push_constant_packets(ice, batch, stage, &push_bos);
6305 crocus_populate_binding_table(ice, batch, stage, false);
6307 crocus_upload_binding_table(ice, batch,
6312 crocus_emit_cmd(batch, GENX(3DSTATE_BINDING_TABLE_POINTERS_VS), ptr) {
6320 crocus_populate_binding_table(ice, batch, stage, true);
6322 crocus_upload_binding_table(ice, batch,
6334 crocus_emit_cmd(batch, GENX(3DSTATE_BINDING_TABLE_POINTERS), ptr) {
6353 crocus_upload_sampler_states(ice, batch, stage);
6360 crocus_emit_cmd(batch, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS), ptr) {
6372 crocus_emit_cmd(batch, GENX(3DSTATE_SAMPLER_STATE_POINTERS), ptr) {
6397 crocus_emit_cmd(batch, GENX(3DSTATE_MULTISAMPLE), ms) {
6426 crocus_emit_cmd(batch, GENX(3DSTATE_SAMPLE_MASK), ms) {
6438 crocus_emit_cmd(batch, GENX(3DSTATE_PS), ps) {
6472 batch->screen->devinfo.max_threads_per_psd - 2;
6474 ps.MaximumNumberofThreads = batch->screen->devinfo.max_wm_threads - 1;
6509 crocus_emit_cmd(batch, GENX(3DSTATE_PS_EXTRA), psx) {
6568 crocus_emit_cmd(batch, GENX(3DSTATE_SO_BUFFER), sob) {
6570 sob.MOCS = crocus_mocs(NULL, &batch->screen->isl_dev);
6579 crocus_emit_cmd(batch, GENX(3DSTATE_SO_BUFFER), sob) {
6583 sob.MOCS = crocus_mocs(res->bo, &batch->screen->isl_dev);
6608 crocus_batch_emit(batch, decl_list, 4 * ((decl_list[0] & 0xff) + 2));
6626 crocus_emit_merge(batch, ice->state.streamout, dynamic_sol,
6631 crocus_emit_cmd(batch, GENX(3DSTATE_STREAMOUT), sol);
6648 uint32_t *clip_ptr = stream_state(batch, GENX(CLIP_STATE_length) * 4, 32, &ice->shaders.clip_offset);
6650 _crocus_pack_state(batch, GENX(CLIP_STATE), clip_ptr, clip) {
6663 clip.NumberofURBEntries = batch->ice->urb.nr_clip_entries;
6664 clip.URBEntryAllocationSize = batch->ice->urb.vsize - 1;
6666 if (batch->ice->urb.nr_clip_entries >= 10) {
6670 assert(batch->ice->urb.nr_clip_entries % 2 == 0);
6677 assert(batch->ice->urb.nr_clip_entries >= 5);
6684 clip.ClipperViewportStatePointer = ro_bo(batch->state.bo, ice->state.clip_vp_address);
6740 crocus_emit_merge(batch, cso_rast->clip, dynamic_clip,
6750 if (batch->screen->devinfo.platform == INTEL_PLATFORM_IVB)
6751 gen7_emit_vs_workaround_flush(batch);
6757 setup_constant_buffers(ice, batch, MESA_SHADER_VERTEX, &push_bos);
6759 emit_push_constant_packets(ice, batch, MESA_SHADER_VERTEX, &push_bos);
6762 crocus_emit_cmd(batch, GENX(3DSTATE_VS), vs)
6764 uint32_t *vs_ptr = stream_state(batch,
6767 _crocus_pack_state(batch, GENX(VS_STATE), vs_ptr, vs)
6772 vs.MaximumNumberofThreads = batch->screen->devinfo.max_vs_threads - 1;
6779 vs.NumberofURBEntries = batch->ice->urb.nr_vs_entries >> (GFX_VER == 5 ? 2 : 0);
6780 vs.URBEntryAllocationSize = batch->ice->urb.vsize - 1;
6783 CLAMP(batch->ice->urb.nr_vs_entries / 2, 1, batch->screen->devinfo.max_vs_threads) - 1;
6785 vs.SamplerStatePointer = ro_bo(batch->state.bo, ice->state.shaders[MESA_SHADER_VERTEX].sampler_offset);
6809 crocus_emit_pipe_control_flush(batch,
6823 setup_constant_buffers(ice, batch, MESA_SHADER_GEOMETRY, &push_bos);
6825 emit_push_constant_packets(ice, batch, MESA_SHADER_GEOMETRY, &push_bos);
6840 if (batch->screen->devinfo.gt == 2 && ice->state.gs_enabled != active)
6841 gen7_emit_cs_stall_flush(batch);
6844 crocus_emit_cmd(batch, GENX(3DSTATE_GS), gs)
6846 uint32_t *gs_ptr = stream_state(batch,
6849 _crocus_pack_state(batch, GENX(GS_STATE), gs_ptr, gs)
6901 GFX_VER == 8 ? (batch->screen->devinfo.max_gs_threads / 2 - 1) :
6902 (batch->screen->devinfo.max_gs_threads - 1);
6955 gs.NumberofURBEntries = batch->ice->urb.nr_gs_entries;
6956 gs.URBEntryAllocationSize = batch->ice->urb.vsize - 1;
6957 gs.MaximumNumberofThreads = batch->ice->urb.nr_gs_entries >= 8 ? 1 : 0;
6966 gs.MaximumNumberofThreads = batch->screen->devinfo.max_gs_threads - 1;
7000 crocus_emit_cmd(batch, GENX(3DSTATE_HS), hs) {
7004 hs.MaximumNumberofThreads = batch->screen->devinfo.max_tcs_threads - 1;
7007 crocus_emit_cmd(batch, GENX(3DSTATE_HS), hs);
7019 crocus_emit_cmd(batch, GENX(3DSTATE_TE), te) {
7027 crocus_emit_cmd(batch, GENX(3DSTATE_DS), ds) {
7030 ds.MaximumNumberofThreads = batch->screen->devinfo.max_tes_threads - 1;
7042 crocus_emit_cmd(batch, GENX(3DSTATE_TE), te);
7043 crocus_emit_cmd(batch, GENX(3DSTATE_DS), ds);
7052 uint32_t *sf_ptr = stream_state(batch,
7055 _crocus_pack_state(batch, GENX(SF_STATE), sf_ptr, sf) {
7062 sf.URBEntryAllocationSize = batch->ice->urb.sfsize - 1;
7063 sf.NumberofURBEntries = batch->ice->urb.nr_sf_entries;
7066 sf.SetupViewportStateOffset = ro_bo(batch->state.bo, ice->state.sf_vp_address);
7069 MIN2(GFX_VER == 5 ? 48 : 24, batch->ice->urb.nr_sf_entries) - 1;
7127 crocus_get_depth_stencil_resources(&batch->screen->devinfo,
7137 crocus_emit_merge(batch, cso->sf, dynamic_sf,
7140 crocus_batch_emit(batch, cso->raster, sizeof(cso->raster));
7154 setup_constant_buffers(ice, batch, MESA_SHADER_FRAGMENT, &push_bos);
7156 emit_push_constant_packets(ice, batch, MESA_SHADER_FRAGMENT, &push_bos);
7159 crocus_emit_cmd(batch, GENX(3DSTATE_WM), wm)
7161 uint32_t *wm_ptr = stream_state(batch,
7166 _crocus_pack_state(batch, GENX(WM_STATE), wm_ptr, wm)
7232 wm.SamplerStatePointer = ro_bo(batch->state.bo,
7276 wm.MaximumNumberofThreads = batch->screen->devinfo.max_wm_threads - 1;
7358 crocus_emit_cmd(batch, GENX(3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP), clamp) {
7368 crocus_emit_sbe(batch, ice);
7387 crocus_emit_merge(batch, cso_blend->ps_blend, dynamic_pb,
7396 crocus_emit_cmd(batch, GENX(3DSTATE_WM_DEPTH_STENCIL), wmds) {
7401 void *ds_map = stream_state(batch,
7404 _crocus_pack_state(batch, GENX(DEPTH_STENCIL_STATE), ds_map, ds) {
7409 crocus_emit_cmd(batch, GENX(3DSTATE_CC_STATE_POINTERS), ptr) {
7414 crocus_emit_cmd(batch, GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS), ptr) {
7425 stream_state(batch, sizeof(struct pipe_scissor_state) * ice->state.num_viewports,
7433 crocus_emit_cmd(batch, GENX(3DSTATE_SCISSOR_STATE_POINTERS), ptr) {
7440 struct isl_device *isl_dev = &batch->screen->isl_dev;
7442 crocus_emit_depth_stall_flushes(batch);
7447 batch_ptr = crocus_get_command_space(batch, isl_dev->ds.size);
7462 crocus_get_depth_stencil_resources(&batch->screen->devinfo, cso->zsbuf->texture, &zres, &sres);
7475 info.depth_address = crocus_command_reloc(batch,
7476 (batch_ptr - batch->command.map) + isl_dev->ds.depth_offset,
7496 info.hiz_address = crocus_command_reloc(batch,
7497 (batch_ptr - batch->command.map) + isl_dev->ds.hiz_offset,
7521 info.stencil_address = crocus_command_reloc(batch,
7522 (batch_ptr - batch->command.map) + isl_dev->ds.stencil_offset,
7536 crocus_emit_cmd(batch, GENX(3DSTATE_POLY_STIPPLE_PATTERN), poly) {
7545 crocus_batch_emit(batch, cso->line_stipple, sizeof(cso->line_stipple));
7550 crocus_emit_cmd(batch, GENX(3DSTATE_VF_TOPOLOGY), topo) {
7559 upload_pipelined_state_pointers(batch, ice->shaders.ff_gs_prog ? true : false, ice->shaders.gs_offset,
7562 crocus_upload_urb_fence(batch);
7564 crocus_emit_cmd(batch, GENX(CS_URB_STATE), cs) {
7574 crocus_emit_cmd(batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
7591 crocus_get_command_space(batch, 4 * (1 + vb_dwords * count));
7592 _crocus_pack_command(batch, GENX(3DSTATE_VERTEX_BUFFERS), map, vb) {
7605 emit_vertex_buffer_state(batch, i, bo,
7615 emit_vertex_buffer_state(batch, i++,
7623 emit_vertex_buffer_state(batch, i++,
7638 crocus_batch_emit(batch, cso->vertex_elements, sizeof(uint32_t) *
7703 crocus_batch_emit(batch, &dynamic_ves, sizeof(uint32_t) *
7709 crocus_batch_emit(batch, cso->vf_instancing, sizeof(uint32_t) *
7728 crocus_batch_emit(batch, &dynamic_vfi[0], sizeof(uint32_t) *
7740 crocus_emit_cmd(batch, GENX(3DSTATE_VF_SGVS), sgv) {
7759 crocus_emit_cmd(batch, GENX(3DSTATE_VF), vf) {
7771 genX(crocus_update_pma_fix)(ice, batch, enable);
7777 gen4_upload_curbe(batch);
7784 struct crocus_batch *batch,
7794 batch->no_wrap = true;
7795 batch->contains_draw = true;
7797 crocus_update_surface_base_address(batch);
7799 crocus_upload_dirty_render_state(ice, batch, draw);
7801 batch->no_wrap = false;
7842 crocus_emit_cmd(batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
7854 ib.MOCS = crocus_mocs(bo, &batch->screen->isl_dev);
7883 crocus_emit_pipe_control_flush(batch,
7889 mi_builder_init(&b, &batch->screen->devinfo, batch);
7912 crocus_batch_emit(batch, &mi_predicate, sizeof(uint32_t));
7919 crocus_load_register_imm64(batch, MI_PREDICATE_SRC1, drawid_offset);
7923 crocus_load_register_mem32(batch, MI_PREDICATE_SRC0,
7926 crocus_load_register_imm32(batch, MI_PREDICATE_SRC0 + 4, 0);
7944 crocus_batch_emit(batch, &mi_predicate, sizeof(uint32_t));
7952 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
7956 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
7960 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
7965 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
7969 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
7974 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
7978 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
7990 crocus_emit_pipe_control_flush(batch,
7995 mi_builder_init(&b, &batch->screen->devinfo, batch);
8005 _crocus_emit_lri(batch, _3DPRIM_START_VERTEX, 0);
8006 _crocus_emit_lri(batch, _3DPRIM_BASE_VERTEX, 0);
8007 _crocus_emit_lri(batch, _3DPRIM_START_INSTANCE, 0);
8008 _crocus_emit_lri(batch, _3DPRIM_INSTANCE_COUNT, draw->instance_count);
8015 crocus_emit_cmd(batch, GENX(3DPRIMITIVE), prim) {
8047 struct crocus_batch *batch,
8051 struct crocus_screen *screen = batch->screen;
8061 crocus_update_surface_base_address(batch);
8066 crocus_populate_binding_table(ice, batch, MESA_SHADER_COMPUTE, false);
8068 crocus_upload_binding_table(ice, batch,
8074 crocus_upload_sampler_states(ice, batch, MESA_SHADER_COMPUTE);
8086 crocus_emit_pipe_control_flush(batch,
8090 crocus_emit_cmd(batch, GENX(MEDIA_VFE_STATE), vfe) {
8144 stream_state(batch,
8152 crocus_emit_cmd(batch, GENX(MEDIA_CURBE_LOAD), curbe) {
8179 crocus_emit_cmd(batch, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), load) {
8183 emit_state(batch, desc, sizeof(desc), 64);
8194 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
8198 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
8202 crocus_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
8209 _crocus_emit_lri(batch, MI_PREDICATE_SRC0 + 4, 0);
8210 crocus_load_register_imm64(batch, MI_PREDICATE_SRC1, 0);
8213 crocus_load_register_mem32(batch, MI_PREDICATE_SRC0, bo, grid_size->offset + 0);
8216 crocus_emit_cmd(batch, GENX(MI_PREDICATE), mip) {
8223 crocus_load_register_mem32(batch, MI_PREDICATE_SRC0, bo, grid_size->offset + 4);
8226 crocus_emit_cmd(batch, GENX(MI_PREDICATE), mip) {
8233 crocus_load_register_mem32(batch, MI_PREDICATE_SRC0, bo, grid_size->offset + 8);
8236 crocus_emit_cmd(batch, GENX(MI_PREDICATE), mip) {
8244 crocus_emit_cmd(batch, GENX(MI_PREDICATE), mip) {
8252 crocus_emit_cmd(batch, GENX(GPGPU_WALKER), ggw) {
8266 crocus_emit_cmd(batch, GENX(MEDIA_STATE_FLUSH), msf);
8268 batch->contains_draw = true;
8474 #define IS_COMPUTE_PIPELINE(batch) (batch->name == CROCUS_BATCH_COMPUTE)
8489 crocus_emit_raw_pipe_control(struct crocus_batch *batch,
8496 UNUSED const struct intel_device_info *devinfo = &batch->screen->devinfo;
8519 crocus_emit_post_sync_nonzero_flush(batch);
8533 bo = batch->ice->workaround_bo;
8534 offset = batch->ice->workaround_offset;
8729 if (IS_COMPUTE_PIPELINE(batch)) {
8779 * to count them within a batch. We currently naively count every 4, and
8786 batch->pipe_controls_since_last_cs_stall = 0;
8790 if (++batch->pipe_controls_since_last_cs_stall == 4) {
8791 batch->pipe_controls_since_last_cs_stall = 0;
8863 crocus_emit_cmd(batch, GENX(PIPE_CONTROL), pc) {
8913 genX(crocus_upload_urb)(struct crocus_batch *batch,
8918 struct crocus_context *ice = batch->ice;
8921 const struct intel_device_info *devinfo = &batch->screen->devinfo;
8950 crocus_emit_cmd(batch, GENX(3DSTATE_URB), urb) {
8970 crocus_emit_mi_flush(batch);
8976 crocus_lost_genx_state(struct crocus_context *ice, struct crocus_batch *batch)
8981 crocus_emit_mi_report_perf_count(struct crocus_batch *batch,
8987 crocus_emit_cmd(batch, GENX(MI_REPORT_PERF_COUNT), mi_rpc) {
9015 * the end of the previous batch buffer. This has been fine so far since
9033 gen7_emit_isp_disable(struct crocus_batch *batch)
9035 crocus_emit_raw_pipe_control(batch, "isp disable",
9039 crocus_emit_raw_pipe_control(batch, "isp disable",
9044 struct crocus_context *ice = batch->ice;
9055 crocus_state_finish_batch(struct crocus_batch *batch)
9058 if (batch->name == CROCUS_BATCH_RENDER) {
9059 crocus_emit_mi_flush(batch);
9060 crocus_emit_cmd(batch, GENX(3DSTATE_CC_STATE_POINTERS), ptr) {
9061 ptr.ColorCalcStatePointer = batch->ice->shaders.cc_offset;
9064 crocus_emit_pipe_control_flush(batch, "hsw wa", PIPE_CONTROL_RENDER_TARGET_FLUSH |
9068 gen7_emit_isp_disable(batch);
9073 crocus_batch_reset_dirty(struct crocus_batch *batch)
9076 pipe_resource_reference(&batch->ice->state.index_buffer.res, NULL);
9078 /* for GEN4/5 need to reemit anything that ends up in the state batch that points to anything in the state batch
9079 * as the old state batch won't still be available.
9081 batch->ice->state.dirty |= CROCUS_DIRTY_DEPTH_BUFFER |
9084 batch->ice->state.dirty |= CROCUS_DIRTY_VERTEX_ELEMENTS | CROCUS_DIRTY_VERTEX_BUFFERS;
9086 batch->ice->state.stage_dirty |= CROCUS_ALL_STAGE_DIRTY_BINDINGS;
9087 batch->ice->state.stage_dirty |= CROCUS_STAGE_DIRTY_SAMPLER_STATES_VS;
9088 batch->ice->state.stage_dirty |= CROCUS_STAGE_DIRTY_SAMPLER_STATES_TES;
9089 batch->ice->state.stage_dirty |= CROCUS_STAGE_DIRTY_SAMPLER_STATES_TCS;
9090 batch->ice->state.stage_dirty |= CROCUS_STAGE_DIRTY_SAMPLER_STATES_GS;
9091 batch->ice->state.stage_dirty |= CROCUS_STAGE_DIRTY_SAMPLER_STATES_PS;
9092 batch->ice->state.stage_dirty |= CROCUS_STAGE_DIRTY_SAMPLER_STATES_CS;
9094 batch->ice->state.stage_dirty |= CROCUS_STAGE_DIRTY_CONSTANTS_VS;
9095 batch->ice->state.stage_dirty |= CROCUS_STAGE_DIRTY_CONSTANTS_TES;
9096 batch->ice->state.stage_dirty |= CROCUS_STAGE_DIRTY_CONSTANTS_TCS;
9097 batch->ice->state.stage_dirty |= CROCUS_STAGE_DIRTY_CONSTANTS_GS;
9098 batch->ice->state.stage_dirty |= CROCUS_STAGE_DIRTY_CONSTANTS_FS;
9099 batch->ice->state.stage_dirty |= CROCUS_STAGE_DIRTY_CONSTANTS_CS;
9101 batch->ice->state.stage_dirty |= CROCUS_STAGE_DIRTY_VS;
9102 batch->ice->state.stage_dirty |= CROCUS_STAGE_DIRTY_GS;
9103 batch->ice->state.stage_dirty |= CROCUS_STAGE_DIRTY_CS;
9104 batch->ice->state.dirty |= CROCUS_DIRTY_CC_VIEWPORT | CROCUS_DIRTY_SF_CL_VIEWPORT;
9108 batch->ice->state.dirty |= CROCUS_DIRTY_GEN6_BLEND_STATE;
9109 batch->ice->state.dirty |= CROCUS_DIRTY_GEN6_SCISSOR_RECT;
9110 batch->ice->state.dirty |= CROCUS_DIRTY_GEN6_WM_DEPTH_STENCIL;
9115 batch->ice->state.dirty |= CROCUS_DIRTY_RASTER;
9116 batch->ice->state.dirty |= CROCUS_DIRTY_GEN4_CURBE;
9117 batch->ice->state.dirty |= CROCUS_DIRTY_CLIP;
9118 batch->ice->state.dirty |= CROCUS_DIRTY_WM;
9122 batch->ice->state.dirty |= CROCUS_DIRTY_STREAMOUT;
9123 batch->ice->state.dirty |= CROCUS_DIRTY_SO_DECL_LIST;
9124 batch->ice->state.dirty |= CROCUS_DIRTY_GEN7_SO_BUFFERS;