Lines Matching defs:base
412 * necessary prior to changing the surface state base adress. We've
414 * command buffers which clear depth, reset state base address, and then
443 /* After re-setting the surface state base address, we have to do some
2638 if (tex->base.target == PIPE_TEXTURE_1D)
2640 else if (tex->base.target == PIPE_TEXTURE_CUBE ||
2641 tex->base.target == PIPE_TEXTURE_CUBE_ARRAY) {
2649 !(GFX_VERx10 == 70 && util_format_is_pure_integer(tex->base.format)))
2656 if (tex->base.target != PIPE_BUFFER)
2657 first_level = tex->base.u.tex.first_level;
2681 /* initialize base object */
2682 isv->base = *tmpl;
2683 isv->base.context = ctx;
2684 isv->base.texture = NULL;
2685 pipe_reference_init(&isv->base.reference, 1);
2686 pipe_resource_reference(&isv->base.texture, tex);
2695 tex = util_format_has_depth(desc) ? &zres->base.b : &sres->base.b;
2699 tex = &sres->shadow->base.b;
2706 if (isv->base.target == PIPE_TEXTURE_CUBE ||
2707 isv->base.target == PIPE_TEXTURE_CUBE_ARRAY)
2808 crocus_resource_finish_aux_import(&screen->base, isv->res);
2812 return &isv->base;
2859 struct pipe_surface *psurf = &surf->base;
2911 crocus_resource_finish_aux_import(&screen->base, res);
2918 res->base.b.target == PIPE_TEXTURE_3D ? 0 : tmpl->u.tex.first_layer,
2919 res->base.b.target == PIPE_TEXTURE_3D ? tmpl->u.tex.first_layer : 0,
2928 .width0 = u_minify(res->base.b.width0, tmpl->u.tex.level),
2929 .height0 = u_minify(res->base.b.height0, tmpl->u.tex.level),
2932 .format = res->base.b.format,
2936 surf->align_res = screen->base.resource_create(&screen->base, &wa_templ);
3073 util_copy_image_view(&iv->base, img);
3096 if (res->base.b.target != PIPE_BUFFER) {
3120 util_range_add(&res->base.b, &res->valid_buffer_range, img->u.buf.offset,
3126 pipe_resource_reference(&iv->base.resource, NULL);
3631 pipe_resource_reference(&ssbo->buffer, &res->base.b);
3641 util_range_add(&res->base.b, &res->valid_buffer_range, ssbo->buffer_offset,
3946 struct pipe_stream_output_target base;
3977 void *val = so->context->buffer_map(so->context, &tgt->offset_res->base.b,
4028 pipe_reference_init(&cso->base.reference, 1);
4029 pipe_resource_reference(&cso->base.buffer, p_res);
4030 cso->base.buffer_offset = buffer_offset;
4031 cso->base.buffer_size = buffer_size;
4032 cso->base.context = ctx;
4034 util_range_add(&res->base.b, &res->valid_buffer_range, buffer_offset,
4045 return &cso->base;
4055 pipe_resource_reference(&cso->base.buffer, NULL);
4073 batch->screen->base.fence_finish(&batch->screen->base, &batch->ice->ctx, out_fence, UINT64_MAX);
4074 batch->screen->base.fence_reference(&batch->screen->base, &out_fence, NULL);
4159 struct crocus_resource *res = (void *) tgt->base.buffer;
4410 max_vertex = MIN2(max_vertex, tgt->base.buffer_size / tgt->stride);
4994 if (res->base.b.target == PIPE_TEXTURE_3D && view.array_len == 1) {
5002 } else if (res->base.b.target == PIPE_TEXTURE_CUBE && GFX_VER == 4) {
5010 } else if (res->base.b.target == PIPE_TEXTURE_1D_ARRAY)
5081 struct crocus_resource *res = (struct crocus_resource *)surf->base.texture;
5084 enum pipe_texture_target target = res->base.b.target;
5108 struct crocus_resource *res = (struct crocus_resource *)surf->base.texture;
5203 if (isv->base.target == PIPE_BUFFER) {
5207 MIN3(isv->base.u.buf.size, isv->res->bo->size - isv->res->offset,
5212 isv->res->offset + isv->base.u.buf.offset, RELOC_32BIT),
5239 struct crocus_resource *res = (struct crocus_resource *)iv->base.resource;
5242 bool write = iv->base.shader_access & PIPE_IMAGE_ACCESS_WRITE;
5244 if (res->base.b.target == PIPE_BUFFER) {
5248 MIN3(iv->base.u.buf.size, res->bo->size - res->offset - iv->base.u.buf.offset,
5253 res->offset + iv->base.u.buf.offset, reloc),
5355 crocus_resource_bo(&buf->base.b),
5479 if (view->base.resource)
5530 /* Set base addresses */
5583 * if you don't set the "Address Modify Enable" bit for the base.
6500 if (wm_prog_data->base.total_scratch) {
6501 struct crocus_bo *bo = crocus_get_scratch_space(ice, wm_prog_data->base.total_scratch, MESA_SHADER_FRAGMENT);
6502 ps.PerThreadScratchSpace = ffs(wm_prog_data->base.total_scratch) - 11;
6574 struct crocus_resource *res = (void *) tgt->base.buffer;
6575 uint32_t start = tgt->base.buffer_offset;
6577 uint32_t end = ALIGN(start + tgt->base.buffer_size, 4);
6592 sob.SurfaceSize = MAX2(tgt->base.buffer_size / 4, 1) - 1;
6594 rw_bo(crocus_resource_bo(&tgt->offset_res->base.b), tgt->offset_offset);
6748 const struct brw_stage_prog_data *prog_data = &vue_prog_data->base;
6776 vs.ConstantURBEntryReadLength = vue_prog_data->base.curb_read_length;
6856 const struct brw_stage_prog_data *prog_data = &gs_prog_data->base.base;
6998 const struct brw_stage_prog_data *prog_data = &tcs_prog_data->base.base;
7017 const struct brw_stage_prog_data *prog_data = &tes_prog_data->base.base;
7180 wm_prog_data->base.dispatch_grf_start_reg;
7195 wm_prog_data->base.dispatch_grf_start_reg;
7212 wm.ConstantURBEntryReadLength = wm_prog_data->base.curb_read_length;
7273 if (wm_prog_data->base.use_alt_mode)
7317 if (wm_prog_data->base.total_scratch) {
7318 struct crocus_bo *bo = crocus_get_scratch_space(ice, wm_prog_data->base.total_scratch,
7320 wm.PerThreadScratchSpace = ffs(wm_prog_data->base.total_scratch) - 11;
7998 ro_bo(crocus_resource_bo(&so->offset_res->base.b), so->offset_offset);
8000 mi_iadd_imm(&b, mi_mem32(addr), -so->base.buffer_offset);
8140 cs_prog_data->base.param[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID);
8299 pipe_resource_reference(&shs->image[i].base.resource, NULL);
8325 assert(res->base.b.target == PIPE_BUFFER);
8344 if (!buffer->is_user_buffer && &res->base.b == buffer->buffer.resource)
8363 (ice->state.so_target[i]->buffer == &res->base.b)) {
8401 .buffer = &res->base.b,
8429 struct crocus_bo *bo = crocus_resource_bo(iv->base.resource);