Lines Matching defs:chan
980 print_chan(const char *msg, const union tgsi_exec_channel *chan)
983 msg, chan->f[0], chan->f[1], chan->f[2], chan->f[3]);
1395 union tgsi_exec_channel *chan)
1416 chan->u[i] = 0;
1419 chan->u[i] = buf[pos];
1435 chan->u[i] = mach->Inputs[pos].xyzw[swizzle].u[i];
1441 chan->u[i] = mach->SystemValue[index->i[i]].xyzw[swizzle].u[i];
1450 chan->u[i] = mach->Temps[index->i[i]].xyzw[swizzle].u[i];
1459 chan->f[i] = mach->Imms[index->i[i]][swizzle];
1468 chan->u[i] = mach->Addrs[index->i[i]].xyzw[swizzle].u[i];
1478 chan->u[i] = mach->Outputs[index->i[i]].xyzw[swizzle].u[i];
1485 chan->u[i] = 0;
1593 union tgsi_exec_channel *chan,
1610 chan);
1615 union tgsi_exec_channel *chan,
1620 fetch_source_d(mach, chan, reg, chan_index);
1624 micro_abs(chan, chan);
1629 micro_neg(chan, chan);
1631 micro_ineg(chan, chan);
1638 const union tgsi_exec_channel *chan,
1700 debug_printf("%f, ", chan->f[i]);
1727 const union tgsi_exec_channel *chan,
1735 dst = store_dest_dstret(mach, chan, reg, chan_index);
1742 dst->i[i] = chan->i[i];
1747 const union tgsi_exec_channel *chan,
1756 dst = store_dest_dstret(mach, chan, reg, chan_index);
1763 dst->i[i] = chan->i[i];
1768 dst->f[i] = fminf(fmaxf(chan->f[i], 0.0f), 1.0f);
1975 unsigned chan,
1979 FETCH(&d, regdsrcx, chan);
1984 FETCH(&d, regdsrcx + 1, chan);
2041 uint chan;
2133 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2134 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2135 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan);
2186 unsigned chan;
2192 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2193 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2194 if (swizzles[chan] >= 2) {
2196 &inst->Dst[0], inst, chan);
2198 store_dest(mach, &r[swizzles[chan]],
2199 &inst->Dst[0], inst, chan);
2219 uint chan;
2313 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2314 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2315 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan);
2326 uint chan;
2390 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2391 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2392 store_dest(mach, &r[swizzles[chan]],
2393 &inst->Dst[0], inst, chan);
2398 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2399 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2400 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan);
2412 uint chan;
2429 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2430 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2431 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan);
2446 uint chan;
2562 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2563 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2564 store_dest(mach, &r[swizzles[chan]],
2565 &inst->Dst[0], inst, chan);
2578 uint chan;
2644 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2645 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2646 store_dest(mach, &r[swizzles[chan]],
2647 &inst->Dst[0], inst, chan);
2661 unsigned chan )
2666 mach->Inputs[attrib].xyzw[chan].f[i] = mach->InterpCoefs[attrib].a0[chan];
2674 UNUSED unsigned chan,
2689 unsigned chan,
2694 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2695 const float dady = mach->InterpCoefs[attrib].dady[chan];
2706 unsigned chan)
2710 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2711 const float dady = mach->InterpCoefs[attrib].dady[chan];
2712 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2714 mach->Inputs[attrib].xyzw[chan].f[0] = a0;
2715 mach->Inputs[attrib].xyzw[chan].f[1] = a0 + dadx;
2716 mach->Inputs[attrib].xyzw[chan].f[2] = a0 + dady;
2717 mach->Inputs[attrib].xyzw[chan].f[3] = a0 + dadx + dady;
2729 unsigned chan,
2734 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2735 const float dady = mach->InterpCoefs[attrib].dady[chan];
2748 unsigned chan )
2752 const float dadx = mach->InterpCoefs[attrib].dadx[chan];
2753 const float dady = mach->InterpCoefs[attrib].dady[chan];
2754 const float a0 = mach->InterpCoefs[attrib].a0[chan] + dadx * x + dady * y;
2757 mach->Inputs[attrib].xyzw[chan].f[0] = a0 / w[0];
2758 mach->Inputs[attrib].xyzw[chan].f[1] = (a0 + dadx) / w[1];
2759 mach->Inputs[attrib].xyzw[chan].f[2] = (a0 + dady) / w[2];
2760 mach->Inputs[attrib].xyzw[chan].f[3] = (a0 + dadx + dady) / w[3];
2767 unsigned chan );
2875 unsigned int chan;
2881 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2882 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2883 store_dest(mach, &dst, &inst->Dst[0], inst, chan);
2894 unsigned int chan;
2897 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2898 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2901 fetch_source(mach, &src, &inst->Src[0], chan, src_datatype);
2902 op(&dst.xyzw[chan], &src);
2905 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2906 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2907 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan);
2922 unsigned int chan;
2929 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2930 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2931 store_dest(mach, &dst, &inst->Dst[0], inst, chan);
2942 unsigned int chan;
2945 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2946 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2949 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2950 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2951 op(&dst.xyzw[chan], &src[0], &src[1]);
2954 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2955 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2956 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan);
2972 unsigned int chan;
2975 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2976 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2979 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
2980 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
2981 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
2982 op(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
2985 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2986 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
2987 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan);
3004 unsigned int chan;
3007 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3008 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3011 fetch_source(mach, &src[0], &inst->Src[0], chan, src_datatype);
3012 fetch_source(mach, &src[1], &inst->Src[1], chan, src_datatype);
3013 fetch_source(mach, &src[2], &inst->Src[2], chan, src_datatype);
3014 fetch_source(mach, &src[3], &inst->Src[3], chan, src_datatype);
3015 op(&dst.xyzw[chan], &src[0], &src[1], &src[2], &src[3]);
3018 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3019 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3020 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan);
3029 unsigned int chan;
3036 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_Z; chan++) {
3037 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
3038 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
3042 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3043 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3044 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan);
3053 unsigned int chan;
3060 for (chan = TGSI_CHAN_Y; chan <= TGSI_CHAN_W; chan++) {
3061 fetch_source(mach, &arg[0], &inst->Src[0], chan, TGSI_EXEC_DATA_FLOAT);
3062 fetch_source(mach, &arg[1], &inst->Src[1], chan, TGSI_EXEC_DATA_FLOAT);
3066 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3067 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3068 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan);
3077 unsigned int chan;
3088 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3089 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3090 store_dest(mach, &arg[2], &inst->Dst[0], inst, chan);
3099 unsigned chan;
3104 for (chan = 0; chan < TGSI_QUAD_SIZE; chan++) {
3105 dst.u[chan] = _mesa_float_to_half(arg[0].f[chan]) |
3106 (_mesa_float_to_half(arg[1].f[chan]) << 16);
3108 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3109 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3110 store_dest(mach, &dst, &inst->Dst[0], inst, chan);
3119 unsigned chan;
3123 for (chan = 0; chan < TGSI_QUAD_SIZE; chan++) {
3124 dst[0].f[chan] = _mesa_half_to_float(arg.u[chan] & 0xffff);
3125 dst[1].f[chan] = _mesa_half_to_float(arg.u[chan] >> 16);
3127 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3128 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3129 store_dest(mach, &dst[chan & 1], &inst->Dst[0], inst, chan);
3150 unsigned int chan;
3153 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3154 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3157 fetch_source(mach, &src[0], &inst->Src[0], chan,
3159 fetch_source(mach, &src[1], &inst->Src[1], chan,
3161 fetch_source(mach, &src[2], &inst->Src[2], chan,
3163 micro_ucmp(&dst.xyzw[chan], &src[0], &src[1], &src[2]);
3166 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3167 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3168 store_dest(mach, &dst.xyzw[chan], &inst->Dst[0], inst, chan);
3391 union tgsi_double_channel *chan,
3403 chan->u[i][0] = src[0].u[i];
3404 chan->u[i][1] = src[1].u[i];
3412 const union tgsi_double_channel *chan,
3426 dst[0].u[i] = chan->u[i][0];
3427 dst[1].u[i] = chan->u[i][1];
3433 if (chan->d[i] < 0.0 || isnan(chan->d[i]))
3435 else if (chan->d[i] > 1.0)
3438 temp.d[i] = chan->d[i];
3575 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3576 if (inst->Dst[1].Register.WriteMask & (1 << chan))
3577 store_dest(mach, &dst_exp, &inst->Dst[1], inst, chan);
3664 uint chan;
3694 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3695 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3696 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan);
3743 for (int chan = 0; chan < load_size / 4; chan++)
3744 rgba[chan].u[j] = *(uint32_t *)(ptr + offset.u[j] + chan * 4);
3748 for (int chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3749 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3750 store_dest(mach, &rgba[chan], &inst->Dst[0], inst, chan);
3882 for (int chan = 0; chan < MIN2(4, size_avail / 4); chan++) {
3883 if (inst->Dst[0].Register.WriteMask & (1 << chan))
3884 memcpy(&invocation_ptr[chan], &value[chan].u[j], 4);
3911 uint unit, chan;
3959 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
3960 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
3961 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan);
3971 uint chan, i;
4062 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
4063 store_dest(mach, &r0, &inst->Dst[0], inst, chan);
4083 int i, chan, j;
4101 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4102 if (inst->Dst[0].Register.WriteMask & (1 << chan)) {
4103 store_dest(mach, &r[chan], &inst->Dst[0], inst, chan);
4121 for (int chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4825 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4826 if (!(inst->Dst[0].Register.WriteMask & (1 << chan)))
4829 fetch_src_file_channel(mach, TGSI_FILE_INPUT, chan, &index, &index2D,
4830 &result[chan]);
4837 unsigned pos = index2D.i[chan] * TGSI_EXEC_MAX_INPUT_ATTRIBS + index.i[chan];
4840 mach->InputSampleOffsetApply[pos](mach, pos, chan, x, y, &result[chan]);
4842 store_dest(mach, &result[chan], &inst->Dst[0], inst, chan);
4865 for (int chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4866 if (!(inst->Dst[0].Register.WriteMask & (1 << chan)))
4869 fetch_src_file_channel(mach, TGSI_FILE_INPUT, chan, &index, &index2D, &result);
4870 mach->InputSampleOffsetApply[pos](mach, pos, chan, ofsx.f[chan], ofsy.f[chan], &result);
4871 store_dest(mach, &result, &inst->Dst[0], inst, chan);
4888 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
4889 if (!(inst->Dst[0].Register.WriteMask & (1 << chan)))
4905 fetch_src_file_channel(mach, TGSI_FILE_INPUT, chan, &index, &index2D,
4906 &result[chan]);
4907 store_dest(mach, &result[chan], &inst->Dst[0], inst, chan);