Lines Matching refs:tiling
73 struct tu_tiling_config *tiling = &fb->tiling[gmem_layout];
76 tiling->tile_count = (VkExtent2D) {
80 tiling->tile0 = (VkExtent2D) {
93 tiling->tile_count.width = 2;
94 tiling->tile_count.height = 2;
95 tiling->tile0.width = util_align_npot(DIV_ROUND_UP(fb->width, 2), tile_align_w);
96 tiling->tile0.height = align(DIV_ROUND_UP(fb->height, 2), tile_align_h);
100 while (tiling->tile0.width > max_tile_width) {
101 tiling->tile_count.width++;
102 tiling->tile0.width =
103 util_align_npot(DIV_ROUND_UP(fb->width, tiling->tile_count.width), tile_align_w);
107 while (tiling->tile0.height > max_tile_height) {
108 tiling->tile_count.height++;
109 tiling->tile0.height =
110 util_align_npot(DIV_ROUND_UP(fb->height, tiling->tile_count.height), tile_align_h);
114 while (tiling->tile0.width * tiling->tile0.height > pass->gmem_pixels[gmem_layout]) {
115 if (tiling->tile0.width > MAX2(tile_align_w, tiling->tile0.height)) {
116 tiling->tile_count.width++;
117 tiling->tile0.width =
118 util_align_npot(DIV_ROUND_UP(fb->width, tiling->tile_count.width), tile_align_w);
121 assert(tiling->tile0.height > tile_align_h);
122 tiling->tile_count.height++;
123 tiling->tile0.height =
124 align(DIV_ROUND_UP(fb->height, tiling->tile_count.height), tile_align_h);
130 tu_tiling_config_update_pipe_layout(struct tu_tiling_config *tiling,
136 tiling->pipe0 = (VkExtent2D) {
140 tiling->pipe_count = tiling->tile_count;
142 while (tiling->pipe_count.width * tiling->pipe_count.height > max_pipe_count) {
143 if (tiling->pipe0.width < tiling->pipe0.height) {
144 tiling->pipe0.width += 1;
145 tiling->pipe_count.width =
146 DIV_ROUND_UP(tiling->tile_count.width, tiling->pipe0.width);
148 tiling->pipe0.height += 1;
149 tiling->pipe_count.height =
150 DIV_ROUND_UP(tiling->tile_count.height, tiling->pipe0.height);
156 tu_tiling_config_update_pipes(struct tu_tiling_config *tiling,
161 tiling->pipe_count.width * tiling->pipe_count.height;
163 .width = (tiling->tile_count.width - 1) % tiling->pipe0.width + 1,
164 .height = (tiling->tile_count.height - 1) % tiling->pipe0.height + 1,
168 assert(max_pipe_count <= ARRAY_SIZE(tiling->pipe_config));
170 for (uint32_t y = 0; y < tiling->pipe_count.height; y++) {
171 for (uint32_t x = 0; x < tiling->pipe_count.width; x++) {
172 const uint32_t pipe_x = tiling->pipe0.width * x;
173 const uint32_t pipe_y = tiling->pipe0.height * y;
174 const uint32_t pipe_w = (x == tiling->pipe_count.width - 1)
176 : tiling->pipe0.width;
177 const uint32_t pipe_h = (y == tiling->pipe_count.height - 1)
179 : tiling->pipe0.height;
180 const uint32_t n = tiling->pipe_count.width * y + x;
182 tiling->pipe_config[n] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x) |
186 tiling->pipe_sizes[n] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w * pipe_h);
190 memset(tiling->pipe_config + used_pipe_count, 0,
195 is_hw_binning_possible(const struct tu_tiling_config *tiling)
201 uint32_t tiles_per_pipe = tiling->pipe0.width * tiling->pipe0.height;
206 tu_tiling_config_update_binning(struct tu_tiling_config *tiling, const struct tu_device *device)
208 tiling->binning_possible = is_hw_binning_possible(tiling);
210 if (tiling->binning_possible) {
211 tiling->binning = (tiling->tile_count.width * tiling->tile_count.height) > 2;
214 tiling->binning = true;
217 tiling->binning = false;
219 tiling->binning = false;
229 struct tu_tiling_config *tiling = &fb->tiling[gmem_layout];
231 tu_tiling_config_update_pipe_layout(tiling, device);
232 tu_tiling_config_update_pipes(tiling, device);
233 tu_tiling_config_update_binning(tiling, device);