Lines Matching defs:nir
16 #include "nir/nir.h"
17 #include "nir/nir_builder.h"
2464 enum tess_primitive_mode primitive_mode = shader->ir3_shader->nir->info.tess._primitive_mode;
2505 .nir_final = ralloc_strdup(pipeline->executables_mem_ctx, variant->disasm_info.nir),
2863 nir_shader *nir[ARRAY_SIZE(stage_infos)] = { NULL };
2865 struct tu_shader *shaders[ARRAY_SIZE(nir)] = { NULL };
2868 stage < ARRAY_SIZE(nir); stage++) {
2875 nir[stage] = tu_spirv_to_nir(builder->device, builder->mem_ctx, stage_info, stage);
2876 if (!nir[stage]) {
2885 if (!nir[MESA_SHADER_FRAGMENT]) {
2891 nir[MESA_SHADER_FRAGMENT] = fs_b.shader;
2896 stage < ARRAY_SIZE(nir); stage++) {
2897 if (!nir[stage])
2901 nir_shader_as_str(nir[stage], pipeline->executables_mem_ctx);
2905 tu_link_shaders(builder, nir, ARRAY_SIZE(nir));
2909 stage < ARRAY_SIZE(nir); stage++) {
2910 if (!nir[stage])
2916 tu_shader_create(builder->device, nir[stage], &keys[stage],
2934 (nir[stage]->info.inputs_read & (1ull << VARYING_SLOT_PRIMITIVE_ID));
2937 BITSET_TEST(nir[stage]->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID);
2956 uint64_t outputs_written = last_shader->ir3_shader->nir->info.outputs_written;
3017 stage < ARRAY_SIZE(nir); stage++) {
3028 stage < ARRAY_SIZE(nir); stage++) {
3073 stage < ARRAY_SIZE(nir); stage++) {
4138 nir_shader *nir = tu_spirv_to_nir(dev, pipeline_mem_ctx, stage_info,
4142 nir_shader_as_str(nir, pipeline->executables_mem_ctx) : NULL;
4145 tu_shader_create(dev, nir, &key, layout, pAllocator);