Lines Matching defs:dev
1607 struct tu_device *dev = cs->device;
1626 mtx_lock(&dev->mutex);
1627 if (!dev->tess_bo)
1628 tu_bo_init_new(dev, &dev->tess_bo, TU_TESS_BO_SIZE, TU_BO_ALLOC_NO_FLAGS);
1629 mtx_unlock(&dev->mutex);
1631 uint64_t tess_factor_iova = dev->tess_bo->iova;
2296 calc_pvtmem_size(struct tu_device *dev, struct tu_pvtmem_config *config,
2301 ALIGN(per_fiber_size * dev->physical_device->info->a6xx.fibers_per_sp, 1 << 12);
2308 return dev->physical_device->info->num_sp_cores * per_sp_size;
2312 tu_setup_pvtmem(struct tu_device *dev,
2322 uint32_t total_size = calc_pvtmem_size(dev, config, pvtmem_bytes);
2326 tu_bo_init_new(dev, &pipeline->pvtmem_bo, total_size,
2338 tu_pipeline_allocate_cs(struct tu_device *dev,
2391 pthread_mutex_lock(&dev->pipeline_mutex);
2392 VkResult result = tu_suballoc_bo_alloc(&pipeline->bo, &dev->pipeline_suballoc,
2394 pthread_mutex_unlock(&dev->pipeline_mutex);
2398 tu_cs_init_suballoc(&pipeline->cs, dev, &pipeline->bo);
2558 struct tu_device *dev)
2572 if (size_info->requiredSubgroupSize == dev->compiler->threadsize_base) {
2575 assert(size_info->requiredSubgroupSize == dev->compiler->threadsize_base * 2);
2697 tu_shaders_init(struct tu_device *dev, const void *key_data, size_t key_size)
2703 if (!vk_multialloc_zalloc(&ma, &dev->vk.alloc,
2708 vk_pipeline_cache_object_init(&dev->vk, &shaders->base,
2742 struct tu_device *dev = container_of(_device, struct tu_device, vk);
2744 tu_shaders_init(dev, key_data, key_size);
2756 shaders->variants[i] = ir3_retrieve_variant(blob, dev->compiler, NULL);
3758 struct tu_device *dev,
3762 pthread_mutex_lock(&dev->pipeline_mutex);
3763 tu_suballoc_bo_free(&dev->pipeline_suballoc, &pipeline->bo);
3764 pthread_mutex_unlock(&dev->pipeline_mutex);
3767 tu_bo_finish(dev, pipeline->pvtmem_bo);
3861 struct tu_device *dev,
3869 .device = dev,
3895 if (unlikely(dev->instance->debug_flags & TU_DEBUG_DYNAMIC) && !rendering_info)
4005 TU_FROM_HANDLE(tu_device, dev, device);
4008 cache = cache ? cache : dev->mem_cache;
4011 tu_pipeline_builder_init_graphics(&builder, dev, cache,
4065 TU_FROM_HANDLE(tu_device, dev, device);
4071 cache = cache ? cache : dev->mem_cache;
4086 pipeline = vk_object_zalloc(&dev->vk, pAllocator, sizeof(*pipeline),
4095 tu_shader_key_init(&key, stage_info, dev);
4100 tu_hash_compute(pipeline_sha1, stage_info, layout, &key, dev->compiler);
4115 if (application_cache_hit && cache != dev->mem_cache) {
4120 if (tu6_shared_constants_enable(layout, dev->compiler)) {
4138 nir_shader *nir = tu_spirv_to_nir(dev, pipeline_mem_ctx, stage_info,
4145 tu_shader_create(dev, nir, &key, layout, pAllocator);
4151 compiled = tu_shaders_init(dev, &pipeline_sha1, sizeof(pipeline_sha1));
4153 tu_shader_destroy(dev, shader, pAllocator);
4164 tu_shader_destroy(dev, shader, pAllocator);
4191 result = tu_pipeline_allocate_cs(dev, pipeline, layout, NULL, v);
4198 tu_setup_pvtmem(dev, pipeline, &pvtmem, v->pvtmem_size, v->pvtmem_per_wave);
4228 vk_object_free(&dev->vk, pAllocator, pipeline);
4269 TU_FROM_HANDLE(tu_device, dev, _device);
4275 tu_pipeline_finish(pipeline, dev, pAllocator);
4276 vk_object_free(&dev->vk, pAllocator, pipeline);
4301 TU_FROM_HANDLE(tu_device, dev, _device);
4319 dev->compiler->threadsize_base * (exe->stats.double_threadsize ? 2 : 1);