Lines Matching defs:const_state
403 const struct ir3_const_state *const_state = ir3_const_state(xs);
404 uint32_t base = const_state->offsets.immediate;
405 int32_t size = DIV_ROUND_UP(const_state->immediates_count, 4);
422 const struct ir3_const_state *const_state = ir3_const_state(xs);
427 size += 4 * const_state->ubo_state.num_enabled;
576 const struct ir3_const_state *const_state = ir3_const_state(xs);
577 uint32_t base = const_state->offsets.immediate;
590 tu_cs_emit_array(cs, const_state->immediates, immediate_size);
593 if (const_state->constant_data_ubo != -1) {
599 CP_LOAD_STATE6_0_DST_OFF(const_state->constant_data_ubo) |
612 const struct ir3_ubo_analysis_state *ubo_state = &const_state->ubo_state;
615 if (ubo_state->range[i].ubo.block != const_state->constant_data_ubo ||
637 if (stage == MESA_SHADER_FRAGMENT && const_state->num_driver_params > 0) {
638 uint32_t base = const_state->offsets.driver_param;
639 int32_t size = DIV_ROUND_UP(const_state->num_driver_params, 4);
915 const struct ir3_const_state *const_state = ir3_const_state(consumer);
916 uint32_t base = const_state->offsets.primitive_map;
1645 uint32_t hs_base = hs->const_state->offsets.primitive_param;
1663 uint32_t ds_base = ds->const_state->offsets.primitive_param;
1677 uint32_t gs_base = gs->const_state->offsets.primitive_param;
3213 link->const_state = *ir3_const_state(v);