Lines Matching refs:cmd
152 tu6_write_lrz_reg(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
155 if (cmd->device->physical_device->info->a6xx.lrz_track_quirk) {
167 tu6_disable_lrz_via_depth_view(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
170 tu6_write_lrz_reg(cmd, cs, A6XX_GRAS_LRZ_DEPTH_VIEW(
176 tu6_write_lrz_reg(cmd, cs, A6XX_GRAS_LRZ_CNTL(
181 tu6_emit_event_write(cmd, cs, LRZ_CLEAR);
182 tu6_emit_event_write(cmd, cs, LRZ_FLUSH);
186 tu_lrz_init_state(struct tu_cmd_buffer *cmd,
191 assert((cmd->device->instance->debug_flags & TU_DEBUG_NOLRZ) ||
199 cmd->device->physical_device->info->a6xx.has_lrz_dir_tracking;
210 cmd->state.lrz.image_view = view;
215 cmd->state.lrz.valid = true;
216 cmd->state.lrz.prev_direction = TU_LRZ_UNKNOWN;
220 cmd->state.lrz.fast_clear = view->image->lrz_fc_size > 0;
222 cmd->state.lrz.gpu_dir_tracking = has_gpu_tracking;
223 cmd->state.lrz.reuse_previous_state = !clears_depth;
232 tu_lrz_init_secondary(struct tu_cmd_buffer *cmd,
236 cmd->device->physical_device->info->a6xx.has_lrz_dir_tracking;
241 if (cmd->device->instance->debug_flags & TU_DEBUG_NOLRZ)
247 cmd->state.lrz.valid = true;
248 cmd->state.lrz.prev_direction = TU_LRZ_UNKNOWN;
249 cmd->state.lrz.gpu_dir_tracking = has_gpu_tracking;
256 cmd->state.lrz.fast_clear = true;
259 cmd->state.lrz.image_view = NULL;
260 cmd->state.lrz.reuse_previous_state = false;
269 tu_lrz_begin_resumed_renderpass(struct tu_cmd_buffer *cmd,
273 memset(&cmd->state.lrz, 0, sizeof(cmd->state.lrz));
276 for (a = 0; a < cmd->state.pass->attachment_count; a++) {
277 if (cmd->state.attachments[a]->image->lrz_height)
281 if (a != cmd->state.pass->attachment_count) {
282 const struct tu_render_pass_attachment *att = &cmd->state.pass->attachments[a];
283 tu_lrz_init_state(cmd, att, cmd->state.attachments[a]);
286 cmd->state.lrz.depth_clear_value = clear;
287 cmd->state.lrz.fast_clear = cmd->state.lrz.fast_clear &&
291 cmd->state.dirty |= TU_CMD_DIRTY_LRZ;
296 tu_lrz_begin_renderpass(struct tu_cmd_buffer *cmd,
299 const struct tu_render_pass *pass = cmd->state.pass;
303 if (cmd->state.attachments[i]->image->lrz_height)
307 if (cmd->device->physical_device->info->a6xx.has_lrz_dir_tracking &&
308 cmd->state.pass->subpass_count > 1 && lrz_img_count > 1) {
313 perf_debug(cmd->device,
318 struct tu_image *image = cmd->state.attachments[i]->image;
319 tu_disable_lrz(cmd, &cmd->cs, image);
327 memset(&cmd->state.lrz, 0, sizeof(cmd->state.lrz));
332 tu_lrz_begin_resumed_renderpass(cmd, clear_values);
334 if (!cmd->state.lrz.valid) {
335 tu6_emit_lrz_buffer(&cmd->cs, NULL);
340 tu_lrz_begin_secondary_cmdbuf(struct tu_cmd_buffer *cmd)
342 memset(&cmd->state.lrz, 0, sizeof(cmd->state.lrz));
343 uint32_t a = cmd->state.subpass->depth_stencil_attachment.attachment;
345 const struct tu_render_pass_attachment *att = &cmd->state.pass->attachments[a];
346 tu_lrz_init_secondary(cmd, att);
351 tu_lrz_tiling_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
358 if (!cmd->state.lrz.image_view)
361 struct tu_lrz_state *lrz = &cmd->state.lrz;
371 tu6_write_lrz_reg(cmd, cs,
384 tu6_disable_lrz_via_depth_view(cmd, cs);
385 tu6_write_lrz_reg(cmd, cs, A6XX_GRAS_LRZ_DEPTH_VIEW(.dword = 0));
388 tu6_write_lrz_reg(cmd, cs,
392 tu6_write_lrz_reg(cmd, cs, A6XX_GRAS_LRZ_CNTL(
402 tu6_emit_event_write(cmd, cs, LRZ_CLEAR);
406 tu6_clear_lrz(cmd, cs, lrz->image_view->image, &lrz->depth_clear_value);
416 tu6_dirty_lrz_fc(cmd, cs, lrz->image_view->image);
422 tu_lrz_tiling_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
424 if (cmd->state.lrz.fast_clear || cmd->state.lrz.gpu_dir_tracking) {
425 tu6_emit_lrz_buffer(cs, cmd->state.lrz.image_view->image);
427 if (cmd->state.lrz.gpu_dir_tracking) {
428 tu6_write_lrz_reg(cmd, &cmd->cs,
429 A6XX_GRAS_LRZ_DEPTH_VIEW(.dword = cmd->state.lrz.image_view->view.GRAS_LRZ_DEPTH_VIEW));
433 tu6_write_lrz_reg(cmd, cs, A6XX_GRAS_LRZ_CNTL(
435 .fc_enable = cmd->state.lrz.fast_clear,
436 .disable_on_wrong_dir = cmd->state.lrz.gpu_dir_tracking,
439 tu6_write_lrz_reg(cmd, cs, A6XX_GRAS_LRZ_CNTL(0));
442 tu6_emit_event_write(cmd, cs, LRZ_FLUSH);
457 tu_lrz_sysmem_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
459 if (!cmd->state.lrz.image_view)
466 struct tu_lrz_state *lrz = &cmd->state.lrz;
468 if (cmd->device->physical_device->info->a6xx.has_lrz_dir_tracking) {
469 tu_disable_lrz(cmd, cs, lrz->image_view->image);
471 tu6_write_lrz_reg(cmd, cs,
479 tu6_write_lrz_reg(cmd, &cmd->cs, A6XX_GRAS_LRZ_CNTL(
483 tu6_emit_event_write(cmd, &cmd->cs, LRZ_CLEAR);
484 tu6_emit_event_write(cmd, &cmd->cs, LRZ_FLUSH);
486 tu6_clear_lrz(cmd, cs, lrz->image_view->image, &lrz->depth_clear_value);
492 tu_lrz_sysmem_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
494 tu6_emit_event_write(cmd, &cmd->cs, LRZ_FLUSH);
499 tu_disable_lrz(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
502 if (!cmd->device->physical_device->info->a6xx.has_lrz_dir_tracking)
509 tu6_disable_lrz_via_depth_view(cmd, cs);
514 tu_lrz_clear_depth_image(struct tu_cmd_buffer *cmd,
521 !cmd->device->physical_device->info->a6xx.has_lrz_dir_tracking)
542 tu6_emit_lrz_buffer(&cmd->cs, image);
544 tu6_write_lrz_reg(cmd, &cmd->cs, A6XX_GRAS_LRZ_DEPTH_VIEW(
550 tu6_write_lrz_reg(cmd, &cmd->cs, A6XX_GRAS_LRZ_CNTL(
556 tu6_emit_event_write(cmd, &cmd->cs, LRZ_CLEAR);
557 tu6_emit_event_write(cmd, &cmd->cs, LRZ_FLUSH);
560 tu6_clear_lrz(cmd, &cmd->cs, image, (const VkClearValue*) pDepthStencil);
565 tu_lrz_disable_during_renderpass(struct tu_cmd_buffer *cmd)
567 assert(cmd->state.pass);
569 cmd->state.lrz.valid = false;
570 cmd->state.dirty |= TU_CMD_DIRTY_LRZ;
572 if (cmd->state.lrz.gpu_dir_tracking) {
573 tu6_write_lrz_reg(cmd, &cmd->cs, A6XX_GRAS_LRZ_CNTL(
637 tu6_calculate_lrz_state(struct tu_cmd_buffer *cmd,
640 struct tu_pipeline *pipeline = cmd->state.pipeline;
641 bool z_test_enable = cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
642 bool z_write_enable = cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
643 bool z_read_enable = cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE;
644 bool z_bounds_enable = cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE;
645 VkCompareOp depth_compare_op = (cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK) >> A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT;
649 if (!cmd->state.lrz.valid) {
657 (cmd->device->instance->debug_flags & TU_DEBUG_NOLRZ))
660 if (!cmd->state.lrz.gpu_dir_tracking && !cmd->state.attachments) {
673 gras_lrz_cntl.fc_enable = cmd->state.lrz.fast_clear;
674 gras_lrz_cntl.dir_write = cmd->state.lrz.gpu_dir_tracking;
675 gras_lrz_cntl.disable_on_wrong_dir = cmd->state.lrz.gpu_dir_tracking;
678 if ((cmd->state.pipeline->dynamic_state_mask & BIT(TU_DYNAMIC_STATE_LOGIC_OP)) &&
679 cmd->state.logic_op_enabled && cmd->state.rop_reads_dst)
682 if ((cmd->state.pipeline->dynamic_state_mask & BIT(TU_DYNAMIC_STATE_COLOR_WRITE_ENABLE)) &&
683 cmd->state.color_write_enable != MASK(cmd->state.pipeline->num_rts))
696 perf_debug(cmd->device, "Invalidating LRZ due to FS");
716 perf_debug(cmd->device, "Invalidating LRZ due to ALWAYS/NOT_EQUAL");
720 perf_debug(cmd->device, "Skipping LRZ due to ALWAYS/NOT_EQUAL");
756 if (cmd->state.lrz.prev_direction != TU_LRZ_UNKNOWN &&
758 cmd->state.lrz.prev_direction != lrz_direction) {
760 perf_debug(cmd->device, "Invalidating LRZ due to direction change");
763 perf_debug(cmd->device, "Skipping LRZ due to direction change");
781 cmd->state.lrz.prev_direction = lrz_direction;
784 bool stencil_test_enable = cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE;
788 (cmd->state.dynamic_stencil_wrmask & 0xff) :
793 ((cmd->state.dynamic_stencil_wrmask & 0xff00) >> 8) :
797 (cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FUNC__MASK) >> A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT;
800 (cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK) >> A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT;
816 perf_debug(cmd->device, "Invalidating LRZ due to stencil write");
819 perf_debug(cmd->device, "Skipping LRZ due to stencil write");
826 cmd->state.lrz.valid = false;
828 if (disable_lrz && cmd->state.lrz.gpu_dir_tracking) {
841 cmd->state.lrz.enabled = cmd->state.lrz.valid && gras_lrz_cntl.enable;
842 if (!cmd->state.lrz.enabled)
849 tu6_emit_lrz(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
851 const uint32_t a = cmd->state.subpass->depth_stencil_attachment.attachment;
852 struct A6XX_GRAS_LRZ_CNTL gras_lrz_cntl = tu6_calculate_lrz_state(cmd, a);
854 tu6_write_lrz_reg(cmd, cs, pack_A6XX_GRAS_LRZ_CNTL(gras_lrz_cntl));