Lines Matching defs:lrz
210 cmd->state.lrz.image_view = view;
215 cmd->state.lrz.valid = true;
216 cmd->state.lrz.prev_direction = TU_LRZ_UNKNOWN;
220 cmd->state.lrz.fast_clear = view->image->lrz_fc_size > 0;
222 cmd->state.lrz.gpu_dir_tracking = has_gpu_tracking;
223 cmd->state.lrz.reuse_previous_state = !clears_depth;
227 * lrz.image_view, so that an LRZ buffer is present (even if LRZ is
247 cmd->state.lrz.valid = true;
248 cmd->state.lrz.prev_direction = TU_LRZ_UNKNOWN;
249 cmd->state.lrz.gpu_dir_tracking = has_gpu_tracking;
256 cmd->state.lrz.fast_clear = true;
259 cmd->state.lrz.image_view = NULL;
260 cmd->state.lrz.reuse_previous_state = false;
264 * actually emitting anything. The lrz state needs to be consistent between
266 * lrz etc.
273 memset(&cmd->state.lrz, 0, sizeof(cmd->state.lrz));
286 cmd->state.lrz.depth_clear_value = clear;
287 cmd->state.lrz.fast_clear = cmd->state.lrz.fast_clear &&
327 memset(&cmd->state.lrz, 0, sizeof(cmd->state.lrz));
334 if (!cmd->state.lrz.valid) {
342 memset(&cmd->state.lrz, 0, sizeof(cmd->state.lrz));
353 /* TODO: If lrz was never valid for the entire renderpass, we could exit
358 if (!cmd->state.lrz.image_view)
361 struct tu_lrz_state *lrz = &cmd->state.lrz;
363 tu6_emit_lrz_buffer(cs, lrz->image_view->image);
365 if (lrz->reuse_previous_state) {
369 assert(lrz->gpu_dir_tracking);
372 A6XX_GRAS_LRZ_DEPTH_VIEW(.dword = lrz->image_view->view.GRAS_LRZ_DEPTH_VIEW));
376 bool invalidate_lrz = !lrz->valid && lrz->gpu_dir_tracking;
386 } else if (lrz->fast_clear || lrz->gpu_dir_tracking) {
387 if (lrz->gpu_dir_tracking) {
389 A6XX_GRAS_LRZ_DEPTH_VIEW(.dword = lrz->image_view->view.GRAS_LRZ_DEPTH_VIEW));
394 .fc_enable = lrz->fast_clear,
395 .disable_on_wrong_dir = lrz->gpu_dir_tracking,
405 if (!lrz->fast_clear && !invalidate_lrz) {
406 tu6_clear_lrz(cmd, cs, lrz->image_view->image, &lrz->depth_clear_value);
415 if (lrz->image_view->image->lrz_fc_size) {
416 tu6_dirty_lrz_fc(cmd, cs, lrz->image_view->image);
424 if (cmd->state.lrz.fast_clear || cmd->state.lrz.gpu_dir_tracking) {
425 tu6_emit_lrz_buffer(cs, cmd->state.lrz.image_view->image);
427 if (cmd->state.lrz.gpu_dir_tracking) {
429 A6XX_GRAS_LRZ_DEPTH_VIEW(.dword = cmd->state.lrz.image_view->view.GRAS_LRZ_DEPTH_VIEW));
435 .fc_enable = cmd->state.lrz.fast_clear,
436 .disable_on_wrong_dir = cmd->state.lrz.gpu_dir_tracking,
444 /* If gpu_dir_tracking is enabled and lrz is not valid blob, at this point,
459 if (!cmd->state.lrz.image_view)
466 struct tu_lrz_state *lrz = &cmd->state.lrz;
469 tu_disable_lrz(cmd, cs, lrz->image_view->image);
474 tu6_emit_lrz_buffer(cs, lrz->image_view->image);
478 if (lrz->fast_clear) {
486 tu6_clear_lrz(cmd, cs, lrz->image_view->image, &lrz->depth_clear_value);
569 cmd->state.lrz.valid = false;
572 if (cmd->state.lrz.gpu_dir_tracking) {
581 /* update lrz state based on stencil-test func:
595 * lrz-test. See:
607 * write is enabled, we need to disable lrz-test, since
625 * effects from stencil test we need to disable lrz-test.
649 if (!cmd->state.lrz.valid) {
660 if (!cmd->state.lrz.gpu_dir_tracking && !cmd->state.attachments) {
670 !(pipeline->lrz.force_disable_mask & TU_LRZ_FORCE_DISABLE_WRITE);
673 gras_lrz_cntl.fc_enable = cmd->state.lrz.fast_clear;
674 gras_lrz_cntl.dir_write = cmd->state.lrz.gpu_dir_tracking;
675 gras_lrz_cntl.disable_on_wrong_dir = cmd->state.lrz.gpu_dir_tracking;
695 if (pipeline->lrz.force_disable_mask & TU_LRZ_FORCE_DISABLE_LRZ) {
756 if (cmd->state.lrz.prev_direction != TU_LRZ_UNKNOWN &&
758 cmd->state.lrz.prev_direction != lrz_direction) {
781 cmd->state.lrz.prev_direction = lrz_direction;
826 cmd->state.lrz.valid = false;
828 if (disable_lrz && cmd->state.lrz.gpu_dir_tracking) {
841 cmd->state.lrz.enabled = cmd->state.lrz.valid && gras_lrz_cntl.enable;
842 if (!cmd->state.lrz.enabled)