Lines Matching refs:state
55 if (cmd->state.tessfactor_addr_set)
60 cmd->state.cache.flush_bits |= TU_CMD_FLAG_WAIT_FOR_IDLE;
61 cmd->state.tessfactor_addr_set = true;
112 tu6_emit_flushes(cmd_buffer, cs, cmd_buffer->state.cache.flush_bits);
113 cmd_buffer->state.cache.flush_bits = 0;
122 if (!cmd_buffer->state.renderpass_cache.flush_bits &&
125 tu6_emit_flushes(cmd_buffer, cs, cmd_buffer->state.renderpass_cache.flush_bits);
126 cmd_buffer->state.renderpass_cache.flush_bits = 0;
130 * blits and draws). This deals with changing CCU state as well as the usual
139 enum tu_cmd_flush_bits flushes = cmd_buffer->state.cache.flush_bits;
145 /* Changing CCU state must involve invalidating the CCU. In sysmem mode,
150 if (ccu_state != cmd_buffer->state.ccu_state) {
151 if (cmd_buffer->state.ccu_state != TU_CMD_CCU_GMEM) {
155 cmd_buffer->state.cache.pending_flush_bits &= ~(
163 cmd_buffer->state.cache.pending_flush_bits &= ~(
170 cmd_buffer->state.cache.flush_bits = 0;
172 if (ccu_state != cmd_buffer->state.ccu_state) {
180 cmd_buffer->state.ccu_state = ccu_state;
206 const struct tu_image_view *iview = cmd->state.attachments[a];
208 &cmd->state.pass->attachments[a];
248 const struct tu_framebuffer *fb = cmd->state.framebuffer;
271 const struct tu_image_view *iview = cmd->state.attachments[a];
276 tu_cs_emit(cs, tu_attachment_gmem_offset(cmd, &cmd->state.pass->attachments[a]));
366 const struct tu_image_view *iview = cmd->state.attachments[a];
375 const struct tu_image_view *iview = cmd->state.attachments[a];
408 const VkRect2D *render_area = &cmd->state.render_area;
487 tu_cs_emit_draw_state(struct tu_cs *cs, uint32_t id, struct tu_draw_state state)
536 tu_cs_emit(cs, CP_SET_DRAW_STATE__0_COUNT(state.size) |
539 COND(!state.size, CP_SET_DRAW_STATE__0_DISABLE));
540 tu_cs_emit_qw(cs, state.iova);
546 const struct tu_framebuffer *fb = cmd->state.framebuffer;
547 const struct tu_tiling_config *tiling = &fb->tiling[cmd->state.gmem_layout];
555 if (cmd->state.rp.xfb_used) {
565 if (cmd->state.rp.has_prim_generated_query_in_rp ||
566 cmd->state.prim_generated_query_running_before_rp) {
582 if (!cmd->state.pass->gmem_pixels[cmd->state.gmem_layout])
585 if (cmd->state.framebuffer->layers > 1)
589 if (cmd->state.render_area.extent.width == 0 ||
590 cmd->state.render_area.extent.height == 0)
593 if (cmd->state.rp.has_tess)
596 if (cmd->state.rp.disable_gmem)
600 if (cmd->state.rp.xfb_used && !cmd->state.tiling->binning_possible)
606 if ((cmd->state.rp.has_prim_generated_query_in_rp ||
607 cmd->state.prim_generated_query_running_before_rp) &&
608 !cmd->state.tiling->binning_possible)
632 if (cmd->state.tiling->binning_possible) {
647 const struct tu_tiling_config *tiling = cmd->state.tiling;
691 const struct tu_framebuffer *fb = cmd->state.framebuffer;
692 const struct tu_image_view *dst = cmd->state.attachments[a];
693 const struct tu_image_view *src = cmd->state.attachments[gmem_a];
695 tu_resolve_sysmem(cmd, cs, src, dst, layer_mask, fb->layers, &cmd->state.render_area);
751 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
752 tu_load_gmem_attachment(cmd, cs, i, cmd->state.tiling->binning, false);
758 const struct tu_render_pass *pass = cmd->state.pass;
771 tu_store_gmem_attachment(cmd, cs, a, a, cmd->state.tiling->binning_possible);
795 cmd->state.dirty |= TU_CMD_DIRTY_DRAW_STATE;
822 cmd->state.cache.pending_flush_bits &=
827 cmd->state.ccu_state = TU_CMD_CCU_SYSMEM;
948 const struct tu_tiling_config *tiling = cmd->state.tiling;
973 const struct tu_tiling_config *tiling = cmd->state.tiling;
1006 const struct tu_framebuffer *fb = cmd->state.framebuffer;
1049 * PROGRAM_BINNING to PROGRAM, which invalidates const state (XS_CONST states)
1093 const struct tu_tiling_config *tiling = cmd->state.tiling;
1121 const struct tu_image_view *iview = cmd->state.attachments[a];
1123 &cmd->state.pass->attachments[a];
1183 gmem_offset = att->gmem_offset_stencil[cmd->state.gmem_layout];
1217 assert(cs.cur == cs.end); /* validate draw state size */
1247 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1254 for (uint32_t i = 0; i < cmd->state.pass->attachment_count; ++i)
1264 const struct tu_framebuffer *fb = cmd->state.framebuffer;
1304 tu6_emit_sysmem_resolves(cmd, cs, cmd->state.subpass);
1321 const struct tu_tiling_config *tiling = cmd->state.tiling;
1334 tu6_emit_render_cntl(cmd, cmd->state.subpass, cs, true);
1384 if (cmd->state.prim_generated_query_running_before_rp)
1389 if (cmd->state.prim_generated_query_running_before_rp)
1398 if (cmd->state.rp.draw_cs_writes_to_cond_pred)
1436 const struct tu_framebuffer *fb = cmd->state.framebuffer;
1437 const struct tu_tiling_config *tiling = cmd->state.tiling;
1441 * state that was known only at the end of the renderpass. They will be
1511 trace_end_render_pass(&cmd->trace, &cmd->cs, cmd->state.framebuffer, cmd->state.tiling);
1517 if (cmd_buffer->state.rp.has_tess)
1543 cmd_buffer->state.pass = NULL;
1544 cmd_buffer->state.subpass = NULL;
1545 cmd_buffer->state.framebuffer = NULL;
1546 cmd_buffer->state.attachments = NULL;
1547 cmd_buffer->state.gmem_layout = TU_GMEM_LAYOUT_COUNT; /* invalid value to prevent looking up gmem offsets */
1548 memset(&cmd_buffer->state.rp, 0, sizeof(cmd_buffer->state.rp));
1551 cmd_buffer->state.lrz.valid = false;
1552 cmd_buffer->state.dirty |= TU_CMD_DIRTY_LRZ;
1764 * tracking the CCU state. It's used for the driver to insert its own command
1781 memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));
1782 cmd_buffer->state.index_size = 0xff; /* dirty restart index */
1783 cmd_buffer->state.line_mode = RECTANGULAR;
1784 cmd_buffer->state.gmem_layout = TU_GMEM_LAYOUT_COUNT; /* dirty value */
1786 tu_cache_init(&cmd_buffer->state.cache);
1787 tu_cache_init(&cmd_buffer->state.renderpass_cache);
1826 cmd_buffer->state.predication_active = cond_rend->conditionalRenderingEnable;
1847 cmd_buffer->state.pass = &cmd_buffer->dynamic_pass;
1848 cmd_buffer->state.subpass = &cmd_buffer->dynamic_subpass;
1850 cmd_buffer->state.pass = tu_render_pass_from_handle(pBeginInfo->pInheritanceInfo->renderPass);
1851 cmd_buffer->state.subpass =
1852 &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];
1855 /* We can't set the gmem layout here, because the state.pass only has
1863 * state is unknown.
1865 cmd_buffer->state.ccu_state = TU_CMD_CCU_UNKNOWN;
1884 cmd->state.vertex_buffers.iova = tu_cs_draw_state(&cmd->sub_cs, &cs, 4 * MAX_VBS).iova;
1888 cmd->state.vb[firstBinding + i].base = 0;
1889 cmd->state.vb[firstBinding + i].size = 0;
1892 cmd->state.vb[firstBinding + i].base = buf->iova + pOffsets[i];
1893 cmd->state.vb[firstBinding + i].size = pSizes ? pSizes[i] : (buf->size - pOffsets[i]);
1897 cmd->state.vb[firstBinding + i].stride = pStrides[i];
1902 A6XX_VFD_FETCH_BASE(i, .qword = cmd->state.vb[i].base),
1903 A6XX_VFD_FETCH_SIZE(i, cmd->state.vb[i].size));
1906 cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
1909 cmd->state.dynamic_state[TU_DYNAMIC_STATE_VB_STRIDE].iova =
1913 tu_cs_emit_regs(&cs, A6XX_VFD_FETCH_STRIDE(i, cmd->state.vb[i].stride));
1915 cmd->state.dirty |= TU_CMD_DIRTY_VB_STRIDE;
1953 if (cmd->state.index_size != index_size)
1958 cmd->state.index_va = buf->iova + offset;
1959 cmd->state.max_index_count = (buf->size - offset) >> index_shift;
1960 cmd->state.index_size = index_size;
2062 cmd->state.desc_sets = tu_cs_draw_state(&cmd->sub_cs, &state_cs, 24);
2063 cmd->state.dirty |= TU_CMD_DIRTY_DESC_SETS_LOAD;
2072 cmd->state.dirty |= TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD;
2083 assert(cs->cur == cs->end); /* validate draw state size */
2087 if (!(cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE)) {
2089 tu_cs_emit_draw_state(&cmd->draw_cs, TU_DRAW_STATE_DESC_SETS, cmd->state.desc_sets);
2195 * presumably there isn't any benefit using a draw state when the
2219 cmd->state.streamout_offset[idx] = offset;
2243 tu_cs_emit_regs(cs, A6XX_VPC_SO_BUFFER_OFFSET(i, cmd->state.streamout_offset[i]));
2247 uint32_t offset = cmd->state.streamout_offset[idx];
2299 uint32_t offset = cmd->state.streamout_offset[idx];
2332 cmd->state.rp.xfb_used = true;
2345 cmd->state.dirty |= TU_CMD_DIRTY_SHADER_CONSTS;
2375 if (cmd_buffer->state.pass) {
2376 tu_flush_all_pending(&cmd_buffer->state.renderpass_cache);
2379 tu_flush_all_pending(&cmd_buffer->state.cache);
2380 cmd_buffer->state.cache.flush_bits |=
2400 assert(id < ARRAY_SIZE(cmd->state.dynamic_state));
2401 cmd->state.dynamic_state[id] = tu_cs_draw_state(&cmd->sub_cs, &cs, size);
2406 if (cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE)
2410 tu_cs_emit_draw_state(&cmd->draw_cs, TU_DRAW_STATE_DYNAMIC + id, cmd->state.dynamic_state[id]);
2424 cmd->state.compute_pipeline = pipeline;
2425 tu_cs_emit_state_ib(&cmd->cs, pipeline->program.state);
2431 cmd->state.pipeline = pipeline;
2432 cmd->state.dirty |= TU_CMD_DIRTY_DESC_SETS_LOAD | TU_CMD_DIRTY_SHADER_CONSTS |
2440 if (!(cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE)) {
2445 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM, pipeline->program.state);
2447 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VI, pipeline->vi.state);
2458 cmd->state.rp.has_tess = true;
2466 /* TODO: Move this packet to pipeline state, since it's constant based on the pipeline. */
2471 if (cmd->state.line_mode != pipeline->line_mode) {
2472 cmd->state.line_mode = pipeline->line_mode;
2481 if (cmd->state.subpass && cmd->state.subpass->samples) {
2482 tu6_emit_msaa(cs, cmd->state.subpass->samples, cmd->state.line_mode);
2487 (pipeline->z_negative_one_to_one != cmd->state.z_negative_one_to_one)) {
2488 cmd->state.z_negative_one_to_one = pipeline->z_negative_one_to_one;
2489 cmd->state.dirty |= TU_CMD_DIRTY_VIEWPORTS;
2492 /* the vertex_buffers draw state always contains all the currently
2495 * note there is a HW optimization which makes it so the draw state
2498 if (cmd->state.vertex_buffers.size != pipeline->num_vbs * 4) {
2499 cmd->state.vertex_buffers.size = pipeline->num_vbs * 4;
2500 cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
2504 cmd->state.dynamic_state[TU_DYNAMIC_STATE_VB_STRIDE].size != pipeline->num_vbs * 2) {
2505 cmd->state.dynamic_state[TU_DYNAMIC_STATE_VB_STRIDE].size = pipeline->num_vbs * 2;
2506 cmd->state.dirty |= TU_CMD_DIRTY_VB_STRIDE;
2512 if ((cmd->state.X & pipeline->X##_mask) != pipeline_bits) { \
2513 cmd->state.X &= ~pipeline->X##_mask; \
2514 cmd->state.X |= pipeline_bits; \
2515 cmd->state.dirty |= TU_CMD_DIRTY_##Y; \
2518 cmd->state.dirty &= ~TU_CMD_DIRTY_##Y; \
2521 /* these registers can have bits set from both pipeline and dynamic state
2523 * if the pipeline doesn't use a dynamic state for the register, then
2525 * state with a dynamic state the next draw.
2536 if ((cmd->state.rb_mrt_control[i] & pipeline->rb_mrt_control_mask) !=
2538 cmd->state.rb_mrt_control[i] &= ~pipeline->rb_mrt_control_mask;
2539 cmd->state.rb_mrt_control[i] |= pipeline->rb_mrt_control[i];
2540 cmd->state.dirty |= TU_CMD_DIRTY_BLEND;
2543 if (cmd->state.rb_mrt_blend_control[i] != pipeline->rb_mrt_blend_control[i]) {
2544 cmd->state.rb_mrt_blend_control[i] = pipeline->rb_mrt_blend_control[i];
2545 cmd->state.dirty |= TU_CMD_DIRTY_BLEND;
2550 if (cmd->state.pipeline_color_write_enable != pipeline->color_write_enable) {
2551 cmd->state.pipeline_color_write_enable = pipeline->color_write_enable;
2552 cmd->state.dirty |= TU_CMD_DIRTY_BLEND;
2554 if (cmd->state.pipeline_blend_enable != pipeline->blend_enable) {
2555 cmd->state.pipeline_blend_enable = pipeline->blend_enable;
2556 cmd->state.dirty |= TU_CMD_DIRTY_BLEND;
2558 if (cmd->state.logic_op_enabled != pipeline->logic_op_enabled) {
2559 cmd->state.logic_op_enabled = pipeline->logic_op_enabled;
2560 cmd->state.dirty |= TU_CMD_DIRTY_BLEND;
2563 cmd->state.rop_reads_dst != pipeline->rop_reads_dst) {
2564 cmd->state.rop_reads_dst = pipeline->rop_reads_dst;
2565 cmd->state.dirty |= TU_CMD_DIRTY_BLEND;
2567 if (cmd->state.dynamic_state[TU_DYNAMIC_STATE_BLEND].size != pipeline->num_rts * 3 + 4) {
2568 cmd->state.dirty |= TU_CMD_DIRTY_BLEND;
2571 cmd->state.dirty &= ~TU_CMD_DIRTY_BLEND;
2575 cmd->state.dirty |= TU_CMD_DIRTY_RB_DEPTH_CNTL;
2586 memcpy(&cmd->state.viewport[firstViewport], pViewports, viewportCount * sizeof(*pViewports));
2587 cmd->state.max_viewport = MAX2(cmd->state.max_viewport, firstViewport + viewportCount);
2593 cmd->state.dirty |= TU_CMD_DIRTY_VIEWPORTS;
2605 memcpy(&cmd->state.scissor[firstScissor], pScissors, scissorCount * sizeof(*pScissors));
2606 cmd->state.max_scissor = MAX2(cmd->state.max_scissor, firstScissor + scissorCount);
2608 cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_SCISSOR, 1 + 2 * cmd->state.max_scissor);
2609 tu6_emit_scissor(&cs, cmd->state.scissor, cmd->state.max_scissor);
2617 cmd->state.gras_su_cntl &= ~A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
2618 cmd->state.gras_su_cntl |= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(lineWidth / 2.0f);
2620 cmd->state.dirty |= TU_CMD_DIRTY_GRAS_SU_CNTL;
2676 update_stencil_mask(&cmd->state.dynamic_stencil_mask, faceMask, compareMask);
2678 tu_cs_emit_regs(&cs, A6XX_RB_STENCILMASK(.dword = cmd->state.dynamic_stencil_mask));
2689 update_stencil_mask(&cmd->state.dynamic_stencil_wrmask, faceMask, writeMask);
2691 tu_cs_emit_regs(&cs, A6XX_RB_STENCILWRMASK(.dword = cmd->state.dynamic_stencil_wrmask));
2693 cmd->state.dirty |= TU_CMD_DIRTY_LRZ;
2704 update_stencil_mask(&cmd->state.dynamic_stencil_ref, faceMask, reference);
2706 tu_cs_emit_regs(&cs, A6XX_RB_STENCILREF(.dword = cmd->state.dynamic_stencil_ref));
2726 cmd->state.gras_su_cntl &=
2730 cmd->state.gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_FRONT;
2732 cmd->state.gras_su_cntl |= A6XX_GRAS_SU_CNTL_CULL_BACK;
2734 cmd->state.dirty |= TU_CMD_DIRTY_GRAS_SU_CNTL;
2742 cmd->state.gras_su_cntl &= ~A6XX_GRAS_SU_CNTL_FRONT_CW;
2745 cmd->state.gras_su_cntl |= A6XX_GRAS_SU_CNTL_FRONT_CW;
2747 cmd->state.dirty |= TU_CMD_DIRTY_GRAS_SU_CNTL;
2756 cmd->state.primtype = tu6_primtype(primitiveTopology);
2781 cmd->state.rb_depth_cntl &= ~A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
2784 cmd->state.rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
2786 cmd->state.dirty |= TU_CMD_DIRTY_RB_DEPTH_CNTL;
2795 cmd->state.rb_depth_cntl &= ~A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
2798 cmd->state.rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
2800 cmd->state.dirty |= TU_CMD_DIRTY_RB_DEPTH_CNTL;
2809 cmd->state.rb_depth_cntl &= ~A6XX_RB_DEPTH_CNTL_ZFUNC__MASK;
2811 cmd->state.rb_depth_cntl |=
2814 cmd->state.dirty |= TU_CMD_DIRTY_RB_DEPTH_CNTL;
2823 cmd->state.rb_depth_cntl &= ~A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE;
2826 cmd->state.rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE;
2828 cmd->state.dirty |= TU_CMD_DIRTY_RB_DEPTH_CNTL;
2837 cmd->state.rb_stencil_cntl &= ~(
2843 cmd->state.rb_stencil_cntl |=
2849 cmd->state.dirty |= TU_CMD_DIRTY_RB_STENCIL_CNTL;
2863 cmd->state.rb_stencil_cntl &= ~(
2869 cmd->state.rb_stencil_cntl |=
2877 cmd->state.rb_stencil_cntl &= ~(
2883 cmd->state.rb_stencil_cntl |=
2890 cmd->state.dirty |= TU_CMD_DIRTY_RB_STENCIL_CNTL;
2899 cmd->state.gras_su_cntl &= ~A6XX_GRAS_SU_CNTL_POLY_OFFSET;
2901 cmd->state.gras_su_cntl |= A6XX_GRAS_SU_CNTL_POLY_OFFSET;
2903 cmd->state.dirty |= TU_CMD_DIRTY_GRAS_SU_CNTL;
2912 cmd->state.primitive_restart_enable = primitiveRestartEnable;
2921 cmd->state.pc_raster_cntl &= ~A6XX_PC_RASTER_CNTL_DISCARD;
2922 cmd->state.vpc_unknown_9107 &= ~A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD;
2924 cmd->state.pc_raster_cntl |= A6XX_PC_RASTER_CNTL_DISCARD;
2925 cmd->state.vpc_unknown_9107 |= A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD;
2928 cmd->state.dirty |= TU_CMD_DIRTY_RASTERIZER_DISCARD;
2937 cmd->state.rb_mrt_control_rop =
2938 tu6_rb_mrt_control_rop(logicOp, &cmd->state.rop_reads_dst);
2940 cmd->state.dirty |= TU_CMD_DIRTY_BLEND;
2970 cmd->state.color_write_enable = color_write_enable;
2971 cmd->state.dirty |= TU_CMD_DIRTY_BLEND;
3412 cmd->state.pass = suspended->state.suspended_pass.pass;
3413 cmd->state.subpass = suspended->state.suspended_pass.subpass;
3414 cmd->state.framebuffer = suspended->state.suspended_pass.framebuffer;
3415 cmd->state.attachments = suspended->state.suspended_pass.attachments;
3416 cmd->state.render_area = suspended->state.suspended_pass.render_area;
3417 cmd->state.gmem_layout = suspended->state.suspended_pass.gmem_layout;
3418 cmd->state.tiling = &cmd->state.framebuffer->tiling[cmd->state.gmem_layout];
3419 cmd->state.lrz = suspended->state.suspended_pass.lrz;
3432 tu_render_pass_state_merge(&cmd->state.rp,
3433 &secondary->pre_chain.state);
3462 cmd->state.rp = secondary->state.rp;
3466 * copy its state to "cmd". This also works instead of tu_append_post_chain(),
3469 * renderpass state.
3486 tu_render_pass_state_merge(&cmd->state.rp,
3487 &secondary->state.rp);
3490 /* Take the current render pass state and save it to "pre_chain" to be
3504 cmd->pre_chain.state = cmd->state.rp;
3518 if (cmd->state.pass) {
3519 tu_flush_all_pending(&cmd->state.renderpass_cache);
3522 tu_flush_all_pending(&cmd->state.cache);
3549 if (!secondary->state.lrz.valid)
3550 cmd->state.lrz.valid = false;
3552 tu_render_pass_state_merge(&cmd->state.rp, &secondary->state.rp);
3554 switch (secondary->state.suspend_resume) {
3563 * in which case we have to update its state.
3565 if (cmd->state.suspend_resume == SR_NONE) {
3566 cmd->state.suspend_resume = SR_IN_PRE_CHAIN;
3580 if (secondary->state.suspend_resume == SR_AFTER_PRE_CHAIN ||
3581 secondary->state.suspend_resume == SR_IN_CHAIN_AFTER_PRE_CHAIN) {
3586 if (cmd->state.suspend_resume == SR_NONE)
3599 switch (cmd->state.suspend_resume) {
3603 * started in the primary, so we have to move the state to
3607 cmd->state.suspend_resume = SR_AFTER_PRE_CHAIN;
3621 if (cmd->state.suspend_resume == SR_IN_CHAIN)
3622 cmd->state.suspend_resume = SR_NONE;
3624 cmd->state.suspend_resume = SR_AFTER_PRE_CHAIN;
3635 if (secondary->state.suspend_resume == SR_IN_CHAIN_AFTER_PRE_CHAIN ||
3636 secondary->state.suspend_resume == SR_IN_CHAIN) {
3644 cmd->state.suspended_pass = secondary->state.suspended_pass;
3646 switch (cmd->state.suspend_resume) {
3648 cmd->state.suspend_resume = SR_IN_CHAIN;
3651 cmd->state.suspend_resume = SR_IN_CHAIN_AFTER_PRE_CHAIN;
3660 cmd->state.index_size = secondary->state.index_size; /* for restart index update */
3662 cmd->state.dirty = ~0u; /* TODO: set dirty only what needs to be */
3664 if (!cmd->state.lrz.gpu_dir_tracking && cmd->state.pass) {
3668 cmd->state.lrz.valid = false;
3676 if (cmd->state.pass) {
3677 tu_cache_init(&cmd->state.renderpass_cache);
3679 tu_cache_init(&cmd->state.cache);
3784 external ? &cmd_buffer->state.cache : &cmd_buffer->state.renderpass_cache;
3806 /* emit mrt/zs/msaa/ubwc state for the subpass that is starting (either at
3812 tu6_emit_zs(cmd, cmd->state.subpass, &cmd->draw_cs);
3813 tu6_emit_mrt(cmd, cmd->state.subpass, &cmd->draw_cs);
3814 if (cmd->state.subpass->samples)
3815 tu6_emit_msaa(&cmd->draw_cs, cmd->state.subpass->samples, cmd->state.line_mode);
3816 tu6_emit_render_cntl(cmd, cmd->state.subpass, &cmd->draw_cs, false);
3818 tu_set_input_attachments(cmd, cmd->state.subpass);
3841 cmd->state.pass = pass;
3842 cmd->state.subpass = pass->subpasses;
3843 cmd->state.framebuffer = fb;
3844 cmd->state.render_area = pRenderPassBegin->renderArea;
3846 cmd->state.attachments =
3848 sizeof(cmd->state.attachments[0]), 8,
3851 if (!cmd->state.attachments) {
3857 cmd->state.attachments[i] = pAttachmentInfo ?
3859 cmd->state.framebuffer->attachments[i].attachment;
3870 cmd->state.renderpass_cache.pending_flush_bits =
3871 cmd->state.cache.pending_flush_bits;
3872 cmd->state.renderpass_cache.flush_bits = 0;
3875 cmd->state.renderpass_cache.flush_bits |= TU_CMD_FLAG_CACHE_INVALIDATE;
3895 cmd->state.pass = &cmd->dynamic_pass;
3896 cmd->state.subpass = &cmd->dynamic_subpass;
3897 cmd->state.framebuffer = &cmd->dynamic_framebuffer;
3898 cmd->state.render_area = pRenderingInfo->renderArea;
3900 cmd->state.attachments = cmd->dynamic_attachments;
3909 cmd->state.attachments[a] = view;
3916 cmd->state.attachments[a] = resolve_view;
3929 cmd->state.attachments[a] = view;
3945 cmd->state.attachments[a] = resolve_view;
3962 cmd->state.rp.disable_gmem = true;
3968 cmd->state.renderpass_cache.pending_flush_bits =
3969 cmd->state.cache.pending_flush_bits;
3970 cmd->state.renderpass_cache.flush_bits = 0;
3974 cmd->state.suspending = suspending;
3975 cmd->state.resuming = resuming;
3982 cmd->state.lrz.valid = false;
3992 cmd->state.suspended_pass.pass = cmd->state.pass;
3993 cmd->state.suspended_pass.subpass = cmd->state.subpass;
3994 cmd->state.suspended_pass.framebuffer = cmd->state.framebuffer;
3995 cmd->state.suspended_pass.render_area = cmd->state.render_area;
3996 cmd->state.suspended_pass.attachments = cmd->state.attachments;
3997 cmd->state.suspended_pass.gmem_layout = cmd->state.gmem_layout;
4004 if (!resuming || cmd->state.suspend_resume == SR_NONE) {
4015 switch (cmd->state.suspend_resume) {
4017 cmd->state.suspend_resume = SR_IN_CHAIN;
4020 cmd->state.suspend_resume = SR_IN_CHAIN_AFTER_PRE_CHAIN;
4030 if (resuming && cmd->state.suspend_resume == SR_NONE)
4031 cmd->state.suspend_resume = SR_IN_PRE_CHAIN;
4047 const struct tu_render_pass *pass = cmd->state.pass;
4049 const struct tu_subpass *last_subpass = cmd->state.subpass;
4051 const struct tu_subpass *subpass = cmd->state.subpass++;
4053 /* Track LRZ valid state
4055 * TODO: Improve this tracking for keeping the state of the past depth/stencil images,
4056 * so if they become active again, we reuse its old state.
4059 cmd->state.lrz.valid = false;
4060 cmd->state.dirty |= TU_CMD_DIRTY_LRZ;
4097 tu_subpass_barrier(cmd, &cmd->state.subpass->start_barrier, false);
4099 if (cmd->state.subpass->feedback_invalidate)
4100 cmd->state.renderpass_cache.flush_bits |= TU_CMD_FLAG_CACHE_INVALIDATE;
4236 cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
4239 (cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK) >> A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT;
4250 cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE;
4253 (cmd->state.pipeline->dynamic_state_mask & BIT(VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) ?
4254 (cmd->state.dynamic_stencil_wrmask & 0xff) :
4255 (cmd->state.pipeline->stencil_wrmask & 0xff);
4258 (cmd->state.pipeline->dynamic_state_mask & BIT(VK_DYNAMIC_STATE_STENCIL_WRITE_MASK)) ?
4259 ((cmd->state.dynamic_stencil_wrmask & 0xff00) >> 8) :
4260 (cmd->state.pipeline->stencil_wrmask & 0xff00) >> 8;
4263 (cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FAIL__MASK) >> A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT;
4265 (cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK) >> A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT;
4267 (cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK) >> A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT;
4269 (cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK) >> A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT;
4271 (cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK) >> A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT;
4273 (cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK) >> A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT;
4294 bool depth_test_enable = cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
4298 if ((cmd->state.pipeline->lrz.fs_has_kill ||
4299 cmd->state.pipeline->subpass_feedback_loop_ds) &&
4301 zmode = (cmd->state.lrz.valid && cmd->state.lrz.enabled)
4306 if (cmd->state.pipeline->lrz.force_late_z || !depth_test_enable)
4310 if (cmd->state.pipeline->lrz.early_fragment_tests)
4323 struct tu_pipeline *pipeline = cmd->state.pipeline;
4324 uint32_t color_write_enable = cmd->state.pipeline_color_write_enable;
4328 color_write_enable &= cmd->state.color_write_enable;
4333 tu_cs_emit(cs, cmd->state.rb_mrt_control[i] |
4334 ((cmd->state.logic_op_enabled ?
4335 cmd->state.rb_mrt_control_rop : 0) &
4337 tu_cs_emit(cs, cmd->state.rb_mrt_blend_control[i]);
4345 if (!(cmd->state.logic_op_enabled && cmd->state.rop_reads_dst))
4346 blend_enable_mask &= cmd->state.pipeline_blend_enable;
4349 tu_cs_emit(cs, cmd->state.sp_blend_cntl |
4354 tu_cs_emit(cs, cmd->state.rb_blend_cntl |
4366 const struct tu_pipeline *pipeline = cmd->state.pipeline;
4369 cmd->state.rp.drawcall_count++;
4371 cmd->state.rp.drawcall_bandwidth_per_sample_sum +=
4372 cmd->state.pipeline->color_bandwidth_per_sample;
4375 const uint32_t depth_bandwidth = cmd->state.pipeline->depth_cpp_per_sample;
4376 if (cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE)
4377 cmd->state.rp.drawcall_bandwidth_per_sample_sum += depth_bandwidth;
4378 if (cmd->state.rb_depth_cntl & A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE)
4379 cmd->state.rp.drawcall_bandwidth_per_sample_sum += depth_bandwidth;
4383 cmd->state.pipeline->stencil_cpp_per_sample;
4384 if (cmd->state.rb_stencil_cntl & A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE)
4385 cmd->state.rp.drawcall_bandwidth_per_sample_sum += stencil_bandwidth * 2;
4391 primitive_restart_enabled = cmd->state.primitive_restart_enable;
4401 if (!(cmd->state.dirty & ~TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD))
4405 cmd->state.dirty & (TU_CMD_DIRTY_LRZ | TU_CMD_DIRTY_RB_DEPTH_CNTL |
4412 cmd->state.lrz_and_depth_plane_state =
4418 if (cmd->state.dirty & TU_CMD_DIRTY_RASTERIZER_DISCARD) {
4420 tu_cs_emit_regs(&cs, A6XX_PC_RASTER_CNTL(.dword = cmd->state.pc_raster_cntl));
4421 tu_cs_emit_regs(&cs, A6XX_VPC_UNKNOWN_9107(.dword = cmd->state.vpc_unknown_9107));
4424 if (cmd->state.dirty & TU_CMD_DIRTY_GRAS_SU_CNTL) {
4426 tu_cs_emit_regs(&cs, A6XX_GRAS_SU_CNTL(.dword = cmd->state.gras_su_cntl));
4429 if (cmd->state.dirty & TU_CMD_DIRTY_RB_DEPTH_CNTL) {
4431 uint32_t rb_depth_cntl = cmd->state.rb_depth_cntl;
4447 if (cmd->state.dirty & TU_CMD_DIRTY_RB_STENCIL_CNTL) {
4449 tu_cs_emit_regs(&cs, A6XX_RB_STENCIL_CONTROL(.dword = cmd->state.rb_stencil_cntl));
4452 if (cmd->state.dirty & TU_CMD_DIRTY_SHADER_CONSTS)
4453 cmd->state.shader_const = tu6_emit_consts(cmd, pipeline, false);
4455 if (cmd->state.dirty & TU_CMD_DIRTY_VIEWPORTS) {
4456 struct tu_cs cs = tu_cmd_dynamic_state(cmd, VK_DYNAMIC_STATE_VIEWPORT, 8 + 10 * cmd->state.max_viewport);
4457 tu6_emit_viewport(&cs, cmd->state.viewport, cmd->state.max_viewport,
4461 if (cmd->state.dirty & TU_CMD_DIRTY_BLEND) {
4463 4 + 3 * cmd->state.pipeline->num_rts);
4469 * and if a draw-state disabling path (CmdClearAttachments 3D fallback) was
4474 * buffer doesn't have a state ib to restore it, and not re-emitting them
4477 if (cmd->state.dirty & TU_CMD_DIRTY_DRAW_STATE) {
4481 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_PROGRAM, pipeline->program.state);
4483 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VI, pipeline->vi.state);
4488 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_CONST, cmd->state.shader_const);
4489 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DESC_SETS, cmd->state.desc_sets);
4491 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VB, cmd->state.vertex_buffers);
4492 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_PARAMS, cmd->state.vs_params);
4493 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_LRZ_AND_DEPTH_PLANE, cmd->state.lrz_and_depth_plane_state);
4495 for (uint32_t i = 0; i < ARRAY_SIZE(cmd->state.dynamic_state); i++) {
4498 cmd->state.dynamic_state[i] :
4507 ((cmd->state.dirty & TU_CMD_DIRTY_SHADER_CONSTS) ? 1 : 0) +
4508 ((cmd->state.dirty & TU_CMD_DIRTY_DESC_SETS_LOAD) ? 1 : 0) +
4509 ((cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS) ? 1 : 0) +
4510 ((cmd->state.dirty & TU_CMD_DIRTY_VS_PARAMS) ? 1 : 0) +
4513 if ((cmd->state.dirty & TU_CMD_DIRTY_VB_STRIDE) &&
4519 if ((cmd->state.dirty & TU_CMD_DIRTY_BLEND) &&
4528 if (cmd->state.dirty & TU_CMD_DIRTY_SHADER_CONSTS)
4529 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_CONST, cmd->state.shader_const);
4530 if (cmd->state.dirty & TU_CMD_DIRTY_DESC_SETS_LOAD)
4532 if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS)
4533 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VB, cmd->state.vertex_buffers);
4536 cmd->state.dynamic_state[TU_DYNAMIC_STATE_VB_STRIDE]);
4540 cmd->state.dynamic_state[TU_DYNAMIC_STATE_BLEND]);
4542 if (cmd->state.dirty & TU_CMD_DIRTY_VS_PARAMS)
4543 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_PARAMS, cmd->state.vs_params);
4546 tu_cs_emit_draw_state(cs, TU_DRAW_STATE_LRZ_AND_DEPTH_PLANE, cmd->state.lrz_and_depth_plane_state);
4554 * compute-related state.
4556 cmd->state.dirty &= TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD;
4563 const struct tu_pipeline *pipeline = cmd->state.pipeline;
4575 primtype = cmd->state.primtype;
4582 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(cmd->state.index_size) |
4613 &cmd->state.pipeline->program.link[MESA_SHADER_VERTEX];
4633 if (cmd->state.vs_params.iova) {
4634 cmd->state.vs_params = (struct tu_draw_state) {};
4635 cmd->state.dirty |= TU_CMD_DIRTY_VS_PARAMS;
4647 if (!(cmd->state.dirty & (TU_CMD_DIRTY_DRAW_STATE | TU_CMD_DIRTY_VS_PARAMS)) &&
4648 vertex_offset == cmd->state.last_vs_params.vertex_offset &&
4649 first_instance == cmd->state.last_vs_params.first_instance) {
4682 cmd->state.last_vs_params.vertex_offset = vertex_offset;
4683 cmd->state.last_vs_params.first_instance = first_instance;
4686 cmd->state.vs_params = (struct tu_draw_state) {entry.bo->iova + entry.offset, entry.size / 4};
4688 cmd->state.dirty |= TU_CMD_DIRTY_VS_PARAMS;
4731 tu_cs_emit_qw(cs, cmd->state.index_va);
4732 tu_cs_emit(cs, cmd->state.max_index_count);
4744 cmd->state.renderpass_cache.flush_bits |=
4745 cmd->state.renderpass_cache.pending_flush_bits & TU_CMD_FLAG_WAIT_FOR_ME;
4746 cmd->state.renderpass_cache.pending_flush_bits &= ~TU_CMD_FLAG_WAIT_FOR_ME;
4799 tu_cs_emit_qw(cs, cmd->state.index_va);
4800 tu_cs_emit(cs, cmd->state.max_index_count);
4865 tu_cs_emit_qw(cs, cmd->state.index_va);
4866 tu_cs_emit(cs, cmd->state.max_index_count);
5041 struct tu_pipeline *pipeline = cmd->state.compute_pipeline;
5053 if (cmd->state.dirty & TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD)
5056 cmd->state.dirty &= ~TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD;
5171 cmd_buffer->state.cache.pending_flush_bits |=
5172 cmd_buffer->state.renderpass_cache.pending_flush_bits;
5173 tu_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier, true);
5175 vk_free(&cmd_buffer->pool->vk.alloc, cmd_buffer->state.attachments);
5187 if (cmd_buffer->state.suspending)
5188 cmd_buffer->state.suspended_pass.lrz = cmd_buffer->state.lrz;
5190 if (!cmd_buffer->state.suspending) {
5194 if (cmd_buffer->state.suspend_resume == SR_IN_PRE_CHAIN) {
5203 if (cmd_buffer->state.resuming && !cmd_buffer->state.suspending) {
5205 switch (cmd_buffer->state.suspend_resume) {
5207 cmd_buffer->state.suspend_resume = SR_NONE;
5211 cmd_buffer->state.suspend_resume = SR_AFTER_PRE_CHAIN;
5231 bool gmem = cmd->state.ccu_state == TU_CMD_CCU_GMEM &&
5232 !cmd->state.pass;
5285 if (cmd->state.pass) {
5314 cmd->state.rp.disable_gmem = true;
5319 cmd->state.pass ? &cmd->state.renderpass_cache : &cmd->state.cache;
5343 assert(!cmd->state.pass);
5404 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs;
5434 cmd->state.predication_active = true;
5436 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs;
5442 if (cmd->state.pass)
5475 cmd->state.predication_active = false;
5477 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs;
5496 struct tu_cs *cs = cmd->state.pass ? &cmd->draw_cs : &cmd->cs;
5498 cmd->state.pass ? &cmd->state.renderpass_cache : &cmd->state.cache;
5532 if (cmd->state.pass) {