Lines Matching defs:tiling
547 const struct tu_tiling_config *tiling = &fb->tiling[cmd->state.gmem_layout];
556 assert(tiling->binning_possible);
567 assert(tiling->binning_possible);
571 return tiling->binning;
600 if (cmd->state.rp.xfb_used && !cmd->state.tiling->binning_possible)
608 !cmd->state.tiling->binning_possible)
632 if (cmd->state.tiling->binning_possible) {
647 const struct tu_tiling_config *tiling = cmd->state.tiling;
652 const uint32_t x1 = tiling->tile0.width * tx;
653 const uint32_t y1 = tiling->tile0.height * ty;
654 const uint32_t x2 = MIN2(x1 + tiling->tile0.width - 1, MAX_VIEWPORT_SIZE - 1);
655 const uint32_t y2 = MIN2(y1 + tiling->tile0.height - 1, MAX_VIEWPORT_SIZE - 1);
668 tu_cs_emit(cs, tiling->pipe_sizes[pipe] |
752 tu_load_gmem_attachment(cmd, cs, i, cmd->state.tiling->binning, false);
771 tu_store_gmem_attachment(cmd, cs, a, a, cmd->state.tiling->binning_possible);
948 const struct tu_tiling_config *tiling = cmd->state.tiling;
951 A6XX_VSC_BIN_SIZE(.width = tiling->tile0.width,
952 .height = tiling->tile0.height));
955 A6XX_VSC_BIN_COUNT(.nx = tiling->tile_count.width,
956 .ny = tiling->tile_count.height));
959 tu_cs_emit_array(cs, tiling->pipe_config, 32);
973 const struct tu_tiling_config *tiling = cmd->state.tiling;
975 tiling->pipe_count.width * tiling->pipe_count.height;
1093 const struct tu_tiling_config *tiling = cmd->state.tiling;
1194 A6XX_TEX_CONST_2_PITCH(tiling->tile0.width * cpp);
1321 const struct tu_tiling_config *tiling = cmd->state.tiling;
1330 tu6_emit_bin_size(cs, tiling->tile0.width, tiling->tile0.height,
1338 tu6_emit_bin_size(cs, tiling->tile0.width, tiling->tile0.height,
1354 tu6_emit_bin_size(cs, tiling->tile0.width, tiling->tile0.height,
1357 if (tiling->binning_possible) {
1361 int pipe_count = tiling->pipe_count.width * tiling->pipe_count.height;
1437 const struct tu_tiling_config *tiling = cmd->state.tiling;
1453 for (uint32_t py = 0; py < tiling->pipe_count.height; py++) {
1454 uint32_t pipe_row = py * tiling->pipe_count.width;
1455 for (uint32_t pipe_row_i = 0; pipe_row_i < tiling->pipe_count.width; pipe_row_i++) {
1458 px = tiling->pipe_count.width - 1 - pipe_row_i;
1462 uint32_t tx1 = px * tiling->pipe0.width;
1463 uint32_t ty1 = py * tiling->pipe0.height;
1464 uint32_t tx2 = MIN2(tx1 + tiling->pipe0.width, tiling->tile_count.width);
1465 uint32_t ty2 = MIN2(ty1 + tiling->pipe0.height, tiling->tile_count.height);
1485 trace_end_render_pass(&cmd->trace, &cmd->cs, fb, tiling);
1511 trace_end_render_pass(&cmd->trace, &cmd->cs, cmd->state.framebuffer, cmd->state.tiling);
3418 cmd->state.tiling = &cmd->state.framebuffer->tiling[cmd->state.gmem_layout];