Lines Matching defs:cache
60 cmd->state.cache.flush_bits |= TU_CMD_FLAG_WAIT_FOR_IDLE;
106 /* "Normal" cache flushes, that don't require any special handling */
112 tu6_emit_flushes(cmd_buffer, cs, cmd_buffer->state.cache.flush_bits);
113 cmd_buffer->state.cache.flush_bits = 0;
116 /* Renderpass cache flushes */
131 * cache flushing.
139 enum tu_cmd_flush_bits flushes = cmd_buffer->state.cache.flush_bits;
155 cmd_buffer->state.cache.pending_flush_bits &= ~(
163 cmd_buffer->state.cache.pending_flush_bits &= ~(
170 cmd_buffer->state.cache.flush_bits = 0;
525 * because the whole point is to cache descriptors which are used by the
822 cmd->state.cache.pending_flush_bits &=
1451 * other row, to improve texture cache locality compared to raster order.
1753 /* Initialize the cache, assuming all necessary flushes have happened but *not*
1757 tu_cache_init(struct tu_cache_state *cache)
1759 cache->flush_bits = 0;
1760 cache->pending_flush_bits = TU_CMD_FLAG_ALL_INVALIDATE;
1763 /* Unlike the public entrypoint, this doesn't handle cache tracking, and
1786 tu_cache_init(&cmd_buffer->state.cache);
2352 tu_flush_all_pending(struct tu_cache_state *cache)
2354 cache->flush_bits |= cache->pending_flush_bits & TU_CMD_FLAG_ALL_FLUSH;
2355 cache->pending_flush_bits &= ~TU_CMD_FLAG_ALL_FLUSH;
2379 tu_flush_all_pending(&cmd_buffer->state.cache);
2380 cmd_buffer->state.cache.flush_bits |=
2975 tu_flush_for_access(struct tu_cache_state *cache,
2982 cache->pending_flush_bits |= TU_CMD_FLAG_ALL_INVALIDATE;
2988 cache->pending_flush_bits |=
2995 cache->pending_flush_bits |= TU_CMD_FLAG_##flush | \
3008 cache->pending_flush_bits |= \
3021 flush_bits |= cache->pending_flush_bits & TU_CMD_FLAG_ALL_FLUSH;
3027 flush_bits |= cache->pending_flush_bits & \
3042 (cache->pending_flush_bits & \
3051 cache->flush_bits |= flush_bits;
3052 cache->pending_flush_bits &= ~flush_bits;
3055 /* When translating Vulkan access flags to which cache is accessed
3356 tu_flush_for_stage(struct tu_cache_state *cache,
3365 if (cache->flush_bits & (TU_CMD_FLAG_ALL_FLUSH | TU_CMD_FLAG_ALL_INVALIDATE))
3387 cache->flush_bits |= TU_CMD_FLAG_WAIT_FOR_IDLE;
3389 cache->pending_flush_bits |= TU_CMD_FLAG_WAIT_FOR_ME;
3522 tu_flush_all_pending(&cmd->state.cache);
3674 * to re-initialize the cache with all pending invalidate bits set.
3679 tu_cache_init(&cmd->state.cache);
3783 struct tu_cache_state *cache =
3784 external ? &cmd_buffer->state.cache : &cmd_buffer->state.renderpass_cache;
3799 tu_flush_for_access(cache, src_flags, dst_flags);
3803 tu_flush_for_stage(cache, src_stage, dst_stage);
3871 cmd->state.cache.pending_flush_bits;
3969 cmd->state.cache.pending_flush_bits;
5171 cmd_buffer->state.cache.pending_flush_bits |=
5266 * means that there may be old, stale cache entries which are in the
5318 struct tu_cache_state *cache =
5319 cmd->state.pass ? &cmd->state.renderpass_cache : &cmd->state.cache;
5320 tu_flush_for_access(cache, src_flags, dst_flags);
5324 tu_flush_for_stage(cache, src_stage, dst_stage);
5497 struct tu_cache_state *cache =
5498 cmd->state.pass ? &cmd->state.renderpass_cache : &cmd->state.cache;
5511 tu_flush_for_access(cache, 0, TU_ACCESS_SYSMEM_WRITE);
5528 if (cache->flush_bits != 0 && is_top_of_pipe) {
5529 cache->flush_bits |= TU_CMD_FLAG_WAIT_FOR_IDLE;
5551 tu_flush_for_access(cache, TU_ACCESS_CP_WRITE, 0);