Lines Matching defs:reg

166    /* We don't create an interval, etc. for the base reg, so just lower the
335 can_rematerialize(struct ir3_register *reg)
337 if (reg->flags & IR3_REG_ARRAY)
339 if (reg->instr->opc != OPC_MOV)
341 if (!(reg->instr->srcs[0]->flags & (IR3_REG_IMMED | IR3_REG_CONST)))
343 if (reg->instr->srcs[0]->flags & IR3_REG_RELATIV)
349 rematerialize(struct ir3_register *reg, struct ir3_instruction *after,
352 d("rematerializing ssa_%u:%u", reg->instr->serialno, reg->name);
355 ir3_instr_create(block, reg->instr->opc, 1, reg->instr->srcs_count);
357 dst->flags |= reg->flags & (IR3_REG_HALF | IR3_REG_ARRAY);
358 for (unsigned i = 0; i < reg->instr->srcs_count; i++) {
360 ir3_src_create(remat, INVALID_REG, reg->instr->srcs[i]->flags);
361 *src = *reg->instr->srcs[i];
364 remat->cat1 = reg->instr->cat1;
366 dst->merge_set = reg->merge_set;
367 dst->merge_set_offset = reg->merge_set_offset;
368 dst->interval_start = reg->interval_start;
369 dst->interval_end = reg->interval_end;
379 struct ir3_register *reg)
381 ir3_reg_interval_init(&interval->interval, reg);
382 interval->dst.flags = reg->flags;
383 interval->dst.def = reg;
387 interval->can_rematerialize = can_rematerialize(reg);
450 unsigned size = reg_size(interval->interval.reg);
451 if (interval->interval.reg->flags & IR3_REG_SHARED) {
454 if (interval->interval.reg->flags & IR3_REG_HALF) {
461 if (ctx->merged_regs || !(interval->interval.reg->flags & IR3_REG_HALF)) {
477 unsigned size = reg_size(interval->interval.reg);
478 if (interval->interval.reg->flags & IR3_REG_SHARED) {
481 if (interval->interval.reg->flags & IR3_REG_HALF) {
487 if (ctx->merged_regs || !(interval->interval.reg->flags & IR3_REG_HALF)) {
577 if (interval->interval.reg->flags & IR3_REG_SHARED)
579 else if (interval->interval.reg->flags & IR3_REG_HALF)
671 get_spill_slot(struct ra_spill_ctx *ctx, struct ir3_register *reg)
673 if (reg->merge_set) {
674 if (reg->merge_set->spill_slot == ~0) {
675 reg->merge_set->spill_slot = ALIGN_POT(ctx->spill_slot,
676 reg->merge_set->alignment);
677 ctx->spill_slot = reg->merge_set->spill_slot + reg->merge_set->size * 2;
679 return reg->merge_set->spill_slot + reg->merge_set_offset * 2;
681 if (reg->spill_slot == ~0) {
682 reg->spill_slot = ALIGN_POT(ctx->spill_slot, reg_elem_size(reg));
683 ctx->spill_slot = reg->spill_slot + reg_size(reg) * 2;
685 return reg->spill_slot;
728 struct ir3_register *reg;
734 reg = materialize_pcopy_src(val, instr, block);
736 reg = val->def;
737 reg->instr->flags &= ~IR3_INSTR_UNUSED;
740 d("spilling ssa_%u:%u to %u", reg->instr->serialno, reg->name,
743 unsigned elems = reg_elems(reg);
747 unsigned src_flags = reg->flags & (IR3_REG_HALF | IR3_REG_IMMED |
753 spill->cat6.type = (reg->flags & IR3_REG_HALF) ? TYPE_U16 : TYPE_U32;
755 src->def = reg;
756 if (reg->flags & IR3_REG_ARRAY) {
757 src->size = reg->size;
758 src->array.id = reg->array.id;
761 src->wrmask = reg->wrmask;
772 if (interval->can_rematerialize && !interval->interval.reg->merge_set)
775 spill(ctx, &interval->dst, get_spill_slot(ctx, interval->interval.reg),
788 d("trying ssa_%u:%u", interval->interval.reg->instr->serialno,
789 interval->interval.reg->name);
807 d("trying ssa_%u:%u", interval->interval.reg->instr->serialno,
808 interval->interval.reg->name);
899 reload(struct ra_spill_ctx *ctx, struct ir3_register *reg,
902 unsigned spill_slot = get_spill_slot(ctx, reg);
904 d("reloading ssa_%u:%u from %u", reg->instr->serialno, reg->name,
907 unsigned elems = reg_elems(reg);
911 dst->flags |= reg->flags & (IR3_REG_HALF | IR3_REG_ARRAY);
925 reload->cat6.type = (reg->flags & IR3_REG_HALF) ? TYPE_U16 : TYPE_U32;
927 if (reg->flags & IR3_REG_ARRAY) {
929 dst->array.id = reg->array.id;
930 dst->size = reg->size;
935 dst->merge_set = reg->merge_set;
936 dst->merge_set_offset = reg->merge_set_offset;
937 dst->interval_start = reg->interval_start;
938 dst->interval_end = reg->interval_end;
959 struct ir3_register *child_reg = child->interval.reg;
962 interval->interval.reg->interval_start) / reg_elem_size(def),
1122 struct ir3_register *reg = rzalloc(ctx, struct ir3_register);
1123 *reg = *def;
1124 reg->name = name;
1125 reg->interval_start = offset;
1126 reg->interval_end = offset + reg_size(def);
1127 reg->merge_set = NULL;
1132 ra_spill_interval_init(interval, reg);
1227 struct ir3_register *temp = temp_interval->interval.reg;
1432 is_live_in_all_preds(ctx, interval->interval.reg, block))
1434 if (interval->interval.reg->merge_set ||
1436 spill_live_in(ctx, interval->interval.reg, block);
1447 is_live_in_all_preds(ctx, interval->interval.reg, block))
1449 spill_live_in(ctx, interval->interval.reg, block);
1465 struct ir3_register *def = interval->interval.reg;
1478 (child->interval.reg->interval_start - def->interval_start) /
1479 reg_elem_size(def), reg_elems(child->interval.reg),
1521 reload_live_in(ctx, interval->interval.reg, block);
1612 struct ir3_register *reg = ctx->live->definitions[name];
1613 struct ra_spill_interval *interval = ctx->intervals[reg->name];
1614 struct reg_or_immed *val = read_live_in(ctx, reg, block, 0);
1654 struct ir3_register *def = interval->interval.reg;
1656 if (interval->interval.reg->merge_set ||
1668 if (!BITSET_TEST(state->live_out, interval->interval.reg->name)) {
1690 struct ir3_register *reg = ctx->live->definitions[name];
1693 reload_live_out(ctx, reg, block);
1727 struct ir3_register *def = interval->interval.reg;
1768 _mesa_hash_table_insert(state->remap, interval->interval.reg, val);
1799 struct ir3_register *reg = ctx->live->definitions[name];
1800 handle_live_in(ctx, block, reg);
1824 struct ir3_register *reg = ctx->live->definitions[name];
1825 add_live_in_phi(ctx, reg, block);