Lines Matching defs:dst
56 struct reg_or_immed dst;
220 ra_foreach_dst (dst, instr) {
221 dst->next_use = tmp_next_use[dst->name];
246 ra_foreach_dst (dst, instr) {
247 tmp_next_use[dst->name] = UINT_MAX;
316 foreach_dst (dst, instr) {
317 dst->spill_slot = ~0;
356 struct ir3_register *dst = __ssa_dst(remat);
357 dst->flags |= reg->flags & (IR3_REG_HALF | IR3_REG_ARRAY);
366 dst->merge_set = reg->merge_set;
367 dst->merge_set_offset = reg->merge_set_offset;
368 dst->interval_start = reg->interval_start;
369 dst->interval_end = reg->interval_end;
374 return dst;
382 interval->dst.flags = reg->flags;
383 interval->dst.def = reg;
541 init_dst(struct ra_spill_ctx *ctx, struct ir3_register *dst)
543 struct ra_spill_interval *interval = ctx->intervals[dst->name];
544 ra_spill_interval_init(interval, dst);
546 interval->next_use_distance = dst->next_use;
553 dst->instr->flags |= IR3_INSTR_UNUSED;
558 insert_dst(struct ra_spill_ctx *ctx, struct ir3_register *dst)
560 struct ra_spill_interval *interval = ctx->intervals[dst->name];
573 if (dst->instr->opc == OPC_META_INPUT && dst->num != INVALID_REG) {
574 physreg_t physreg = ra_reg_get_physreg(dst);
575 physreg_t max = physreg + reg_size(dst);
627 finish_dst(struct ra_spill_ctx *ctx, struct ir3_register *dst)
629 struct ra_spill_interval *interval = ctx->intervals[dst->name];
634 remove_dst(struct ra_spill_ctx *ctx, struct ir3_register *dst)
636 struct ra_spill_interval *interval = ctx->intervals[dst->name];
712 struct ir3_register *dst = __ssa_dst(mov);
713 dst->flags |= src->flags & IR3_REG_HALF;
721 return dst;
775 spill(ctx, &interval->dst, get_spill_slot(ctx, interval->interval.reg),
858 struct ir3_register *dst = __ssa_dst(split);
859 dst->flags |= def->flags & IR3_REG_HALF;
863 add_to_merge_set(def->merge_set, dst,
867 return dst;
884 struct ir3_register *dst = __ssa_dst(collect);
885 dst->flags |= parent_def->flags & IR3_REG_HALF;
886 dst->wrmask = MASK(elems);
887 add_to_merge_set(parent_def->merge_set, dst, parent_def->merge_set_offset);
895 return dst;
910 struct ir3_register *dst = __ssa_dst(reload);
911 dst->flags |= reg->flags & (IR3_REG_HALF | IR3_REG_ARRAY);
919 dst->flags |= IR3_REG_EARLY_CLOBBER;
928 dst->array.offset = 0;
929 dst->array.id = reg->array.id;
930 dst->size = reg->size;
932 dst->wrmask = MASK(elems);
935 dst->merge_set = reg->merge_set;
936 dst->merge_set_offset = reg->merge_set_offset;
937 dst->interval_start = reg->interval_start;
938 dst->interval_end = reg->interval_end;
943 return dst;
953 interval->dst.flags = def->flags;
954 interval->dst.def = def;
981 interval->dst.flags = def->flags;
982 interval->dst.def = extract(
983 parent->dst.def, (def->interval_start - parent->dst.def->interval_start) /
989 struct ir3_register *dst;
991 dst = rematerialize(def, instr, block);
993 dst = reload(ctx, def, instr, block);
995 rewrite_src_interval(ctx, interval, dst, instr, block);
1017 set_src_val(src, &interval->dst);
1039 ra_foreach_dst (dst, instr) {
1040 init_dst(ctx, dst);
1055 ra_foreach_dst (dst, instr) {
1056 struct ir3_register *tied_src = dst->tied;
1058 (dst->flags & IR3_REG_EARLY_CLOBBER))
1059 insert_dst(ctx, dst);
1079 ra_foreach_dst (dst, instr) {
1080 insert_dst(ctx, dst);
1102 ra_foreach_dst (dst, instr) {
1103 finish_dst(ctx, dst);
1196 foreach_dst (dst, pcopy) {
1197 struct ra_spill_interval *dst_interval = ctx->intervals[dst->name];
1198 ra_spill_interval_init(dst_interval, dst);
1203 struct ir3_register *dst = pcopy->dsts[i];
1210 src->def->merge_set == dst->merge_set &&
1211 src->def->merge_set_offset == dst->merge_set_offset) {
1213 struct ra_spill_interval *dst_interval = ctx->intervals[dst->name];
1222 dst_interval->dst = src_interval->dst;
1226 create_temp_interval(ctx, dst);
1238 temp_interval->dst = src_interval->dst;
1253 struct ir3_register *dst = pcopy->dsts[i];
1256 src->def->merge_set == dst->merge_set &&
1257 src->def->merge_set_offset == dst->merge_set_offset)
1260 struct ra_spill_interval *dst_interval = ctx->intervals[dst->name];
1270 dst_interval->dst.flags = src->flags;
1271 dst_interval->dst.const_num = src->num;
1273 dst_interval->dst.flags = src->flags;
1274 dst_interval->dst.uimm = src->uim_val;
1284 dst_interval->dst = temp_interval->dst;
1558 interval->dst.def = cur_def;
1559 interval->dst.flags = cur_def->flags;
1565 struct ir3_register *dst = __ssa_dst(phi);
1566 dst->flags |= def->flags & (IR3_REG_HALF | IR3_REG_ARRAY);
1567 dst->size = def->size;
1568 dst->wrmask = def->wrmask;
1570 dst->interval_start = def->interval_start;
1571 dst->interval_end = def->interval_end;
1572 dst->merge_set = def->merge_set;
1573 dst->merge_set_offset = def->merge_set_offset;
1578 struct ir3_register *src = ir3_src_create(phi, INVALID_REG, dst->flags);
1593 interval->dst.def = dst;
1594 interval->dst.flags = dst->flags;
1616 interval->dst = *val;
1658 spill(ctx, &interval->dst, get_spill_slot(ctx, def), NULL, block);
1715 set_src_val(instr->srcs[pred_idx], &interval->dst);
1764 if (!(interval->dst.flags & IR3_REG_SSA) ||
1765 interval->dst.def) {
1767 *val = interval->dst;
2033 ra_foreach_dst (dst, instr) {
2034 dst->merge_set = NULL;
2035 dst->merge_set_offset = 0;
2046 struct ir3_register *dst = instr->dsts[0];
2049 src->def->interval_start < dst->interval_end &&
2050 dst->interval_start < src->def->interval_end) {
2051 ir3_force_merge(dst, src->def,
2052 src->def->interval_start - dst->interval_start);