Lines Matching defs:regid
483 /* Represents half register in regid */
582 * + From the vert shader, we only need the output regid
598 uint8_t regid;
623 uint8_t regid;
1021 uint8_t regid;
1047 if (regid_ != regid(63, 0)) {
1052 l->var[i].regid = regid_;
1071 const unsigned default_regid = pack_vs_out ? regid(63, 0) : regid(0, 0);
1106 k >= 0 ? vs->outputs[k].regid : default_regid,
1117 uint32_t regid = so->outputs[j].regid;
1119 regid |= HALF_REG_ID;
1120 return regid;
1122 return regid(63, 0);
1139 return so->inputs[j].regid;
1140 return regid(63, 0);