Lines Matching defs:regid
69 * regid's might not even be valid)
77 if (v->inputs[i].regid >= regid(48, 0))
82 int32_t regid = v->inputs[i].regid + n;
85 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
87 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
90 v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
97 if (!VALIDREG(v->outputs[i].regid))
99 int32_t regid = v->outputs[i].regid + 3;
102 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
104 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
107 v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
113 int32_t regid = v->sampler_prefetch[i].dst + n;
116 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
118 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
121 v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
690 if (r != regid(63, 0)) {
701 uint32_t regid;
702 regid = ir3_find_output_regid(so, slot);
703 dump_reg(out, name, regid);
786 uint8_t regid;
793 regid = reg->num;
795 (reg->flags & IR3_REG_HALF) ? "h" : "", (regid >> 2),
796 "xyzw"[regid & 0x3], i);
832 uint8_t regid = so->outputs[i].regid;
834 fprintf(out, " %s%d.%c (%s)", reg_type, (regid >> 2), "xyzw"[regid & 0x3],
841 uint8_t regid = so->inputs[i].regid;
842 fprintf(out, " r%d.%c (%s slot=%d cm=%x,il=%u,b=%u)", (regid >> 2),
843 "xyzw"[regid & 0x3], input_name(so, i), so -> inputs[i].slot,
957 ir3_link_add(l, v->outputs[k].slot, v->outputs[k].regid,