Lines Matching refs:scheduled
97 struct ir3_instruction *scheduled; /* last scheduled instr */
114 /* We order the scheduled (sy)/(ss) producers, and keep track of the
134 * scheduled.
149 * as any one of the src's is scheduled.
290 ctx->scheduled = instr;
364 /* there is at least one kill which could be scheduled, except
368 /* there is at least one instruction that could be scheduled,
392 /* could an instruction be scheduled if specified ssa src was scheduled? */
398 /* if dependency not scheduled, we aren't ready yet: */
404 /* Instructions not in the current block can never be scheduled.
423 * write until another "normal" instruction has been scheduled.
450 /* nothing could be scheduled, so keep looking: */
467 /* nothing could be scheduled, so keep looking: */
495 * bary.f is scheduled. The hw seems unhappy if the thread
542 * prefer to get these scheduled earlier, to unlock varying
577 /* find net change to live values if instruction were scheduled: */
711 /* Prioritize instrs which free up regs and can be scheduled with no
834 * - phi nodes and inputs must be scheduled first
835 * - split should be scheduled first, so that the vector value is
930 /* skip instructions already scheduled: */
940 /* original addr is scheduled, but new one isn't: */
945 * already scheduled:
979 /* skip instructions already scheduled: */
992 /* original pred is scheduled, but new one isn't: */
997 * already scheduled:
1007 /* original pred is scheduled, but new one isn't: */
1129 /* NOTE that all inputs must be scheduled before a kill, so
1214 * but it should not be scheduled on top of any other input (but can be
1241 /* Since we've scheduled a "real" instruction, we can now
1329 /* does instruction 'prior' need to be scheduled before 'instr'? */
1368 /* add dependencies on previous instructions that must be scheduled
1390 * that must be scheduled after the current instruction:
1414 * (1) barriers are scheduled in the right order wrt instructions related
1417 * (2) reads that come before a write actually get scheduled before the