Lines Matching defs:def
70 * SSA def assigned to it plus an offset into that definition, and when
80 struct ir3_register *def;
158 if (dst->def == UNKNOWN) {
160 return src->def != UNKNOWN;
161 } else if (dst->def == OVERDEF) {
164 if (src->def == UNKNOWN)
166 else if (src->def == OVERDEF) {
170 if (dst->def != src->def || dst->offset != src->offset) {
171 dst->def = OVERDEF;
226 .def = dst,
264 .def = dst,
297 .def = dst,
368 struct ir3_instruction *instr = state->def->instr;
371 struct ir3_register *new_def = instr->srcs[0]->def;
374 .def = new_def,
380 unsigned src_idx = state->offset / reg_elem_size(state->def);
381 unsigned src_offset = state->offset % reg_elem_size(state->def);
382 struct ir3_register *new_def = instr->srcs[src_idx]->def;
385 .def = new_def,
397 if (instr->dsts[i] == state->def) {
404 struct ir3_register *new_def = instr->srcs[dst_idx]->def;
406 state->def = new_def;
422 if (state->def == UNDEF) {
424 } else if (state->def == OVERDEF) {
429 assert(state->def != UNKNOWN);
431 fprintf(stderr, "ssa_%u:%u(%sr%u.%c) + %u", state->def->instr->serialno,
432 state->def->name, (state->def->flags & IR3_REG_HALF) ? "h" : "",
433 state->def->num / 4, "xyzw"[state->def->num % 4],
446 .def = src->def,
453 if (expected.def != actual.def || expected.offset != actual.offset) {
457 src->def->instr->serialno, src->def->name, i);
503 if (instr->srcs[pred_idx]->def)
517 start->full.regs[i].def = UNDEF;
519 start->half.regs[i].def = UNDEF;
521 start->shared.regs[i].def = UNDEF;