Lines Matching refs:node
96 struct ir3_postsched_node *node = instr->data;
97 return node->has_sy_src;
103 struct ir3_postsched_node *node = instr->data;
104 return node->has_ss_src;
114 list_delinit(&instr->node);
136 list_addtail(&instr->node, &instr->block->instr_list);
350 /* Track the mapping between sched node (instruction) that last
394 struct ir3_postsched_node *node, unsigned num, int src_n,
403 unsigned d_soft = ir3_delayslots(dep->instr, node->instr, src_n, true);
404 d = ir3_delayslots_with_repeat(dep->instr, node->instr, dst_n, src_n);
405 node->delay = MAX2(node->delay, d_soft);
407 node->has_sy_src = true;
409 node->has_ss_src = true;
412 add_dep(state, dep, node, d);
414 dep_reg(state, num) = node;
425 * it corresponds to node->instr->srcs[src_n]. If src_n is negative, then
430 struct ir3_postsched_node *node, const struct ir3_register *reg,
440 add_single_reg_dep(state, node, num, src_n, dst_n);
443 add_single_reg_dep(state, node, 2 * num + 0, src_n, dst_n);
444 add_single_reg_dep(state, node, 2 * num + 1, src_n, dst_n);
449 add_single_reg_dep(state, node, num, src_n, dst_n);
455 struct ir3_postsched_node *node)
460 foreach_src_n (reg, i, node->instr) {
467 add_reg_dep(state, node, reg, reg->array.base + j, i, -1);
472 add_reg_dep(state, node, reg, reg->num + b, i, -1);
480 foreach_dst_n (reg, i, node->instr) {
486 add_reg_dep(state, node, reg, reg->array.base + j, -1, i);
491 add_reg_dep(state, node, reg, reg->num + b, -1, i);
538 sched_dag_max_delay_cb(struct dag_node *node, void *state)
540 struct ir3_postsched_node *n = (struct ir3_postsched_node *)node;
658 list_delinit(&instr->node);
739 list_delinit(&instr->node);