Lines Matching refs:instr
54 * @instr: the mov to consider removing
55 * @dst_instr: the instruction consuming the mov (instr)
61 is_eligible_mov(struct ir3_instruction *instr,
64 if (is_same_type_mov(instr)) {
65 struct ir3_register *dst = instr->dsts[0];
66 struct ir3_register *src = instr->srcs[0];
107 (!cond->address || cond->address->def->instr->block == cmp->block);
160 lower_immed(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr, unsigned n,
169 if (!ir3_valid_flags(instr, n, new_flags))
178 (is_cat2_float(instr->opc) || is_cat3_float(instr->opc)) ? true : false;
243 instr->srcs[n] = reg;
249 unuse(struct ir3_instruction *instr)
251 assert(instr->use_count > 0);
253 if (--instr->use_count == 0) {
254 struct ir3_block *block = instr->block;
256 instr->barrier_class = 0;
257 instr->barrier_conflict = 0;
263 assert(block->keeps[i] != instr);
274 try_swap_mad_two_srcs(struct ir3_instruction *instr, unsigned new_flags)
276 if (!is_mad(instr->opc))
284 if (instr->cat3.swapped)
301 instr->cat3.swapped = true;
306 swap(instr->srcs[0], instr->srcs[1]);
310 ir3_valid_flags(instr, 0, new_flags) &&
312 ir3_valid_flags(instr, 1, instr->srcs[1]->flags);
316 swap(instr->srcs[0], instr->srcs[1]);
346 reg_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr,
351 if (is_eligible_mov(src, instr, true)) {
356 if (!is_valid_shared_copy(instr, src, src_reg))
361 if (ir3_valid_flags(instr, n, new_flags)) {
369 instr->barrier_class |= src->barrier_class;
370 instr->barrier_conflict |= src->barrier_conflict;
373 reg->def->instr->use_count++;
379 opc_cat(instr->opc) != 0) {
384 if (!is_valid_shared_copy(instr, src, src_reg))
392 if (!ir3_valid_flags(instr, n, new_flags)) {
394 if (lower_immed(ctx, instr, n, src_reg, new_flags))
404 if ((n == 1) && try_swap_mad_two_srcs(instr, new_flags)) {
424 conflicts(instr->address, reg->def->instr->address))
429 is_subgroup_cond_mov_macro(instr))
436 if ((opc_cat(instr->opc) == 3) && (n == 2) &&
448 if (is_meta(instr))
450 if (instr->opc == OPC_MOV && !type_float(instr->cat1.src_type))
452 if (!is_cat2_float(instr->opc) && !is_cat3_float(instr->opc))
459 if (is_cat2_float(instr->opc) || is_cat3_float(instr->opc))
461 if (instr->opc == OPC_MOV && type_float(instr->cat1.src_type))
465 src_reg = ir3_reg_clone(instr->block->shader, src_reg);
467 instr->srcs[n] = src_reg;
470 ir3_instr_set_address(instr, reg->def->instr->address->def->instr);
478 assert((opc_cat(instr->opc) == 1) ||
479 (opc_cat(instr->opc) == 2) ||
480 (opc_cat(instr->opc) == 6) ||
481 is_meta(instr) ||
482 (is_mad(instr->opc) && (n == 0)));
484 if ((opc_cat(instr->opc) == 2) &&
485 !ir3_cat2_int(instr->opc)) {
489 return lower_immed(ctx, instr, n, src_reg, new_flags);
502 if (ir3_valid_flags(instr, n, new_flags) &&
503 ir3_valid_immediate(instr, iim_val)) {
505 src_reg = ir3_reg_clone(instr->block->shader, src_reg);
508 instr->srcs[n] = src_reg;
513 return lower_immed(ctx, instr, n, src_reg, new_flags);
527 eliminate_output_mov(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
529 if (is_eligible_mov(instr, NULL, false)) {
530 struct ir3_register *reg = instr->srcs[0];
538 return instr;
546 instr_cp(struct ir3_cp_ctx *ctx, struct ir3_instruction *instr)
548 if (instr->srcs_count == 0)
551 if (ir3_instr_check_mark(instr))
558 foreach_src_n (reg, n, instr) {
573 if (is_meta(instr) &&
581 progress |= reg_cp(ctx, instr, reg, n);
592 if (instr->opc == OPC_MOV && (instr->srcs[0]->flags & IR3_REG_IMMED) &&
593 instr->cat1.src_type != instr->cat1.dst_type &&
597 full_type(instr->cat1.src_type) == TYPE_U32 &&
598 full_type(instr->cat1.dst_type) == TYPE_U32) {
599 uint32_t uimm = instr->srcs[0]->uim_val;
600 if (instr->cat1.dst_type == TYPE_U16)
602 instr->srcs[0]->uim_val = uimm;
603 if (instr->dsts[0]->flags & IR3_REG_HALF)
604 instr->srcs[0]->flags |= IR3_REG_HALF;
606 instr->srcs[0]->flags &= ~IR3_REG_HALF;
607 instr->cat1.src_type = instr->cat1.dst_type;
614 if ((instr->opc == OPC_CMPS_S) && is_foldable_double_cmp(instr)) {
615 struct ir3_instruction *cond = ssa(instr->srcs[0]);
620 instr->opc = cond->opc;
621 instr->flags = cond->flags;
622 instr->cat2 = cond->cat2;
624 ir3_instr_set_address(instr, cond->address->def->instr);
625 instr->srcs[0] = ir3_reg_clone(ctx->shader, cond->srcs[0]);
626 instr->srcs[1] = ir3_reg_clone(ctx->shader, cond->srcs[1]);
627 instr->barrier_class |= cond->barrier_class;
628 instr->barrier_conflict |= cond->barrier_conflict;
643 if (is_tex(instr) && (instr->flags & IR3_INSTR_S2EN) &&
644 !(instr->flags & IR3_INSTR_B) &&
649 struct ir3_instruction *samp_tex = ssa(instr->srcs[0]);
658 instr->flags &= ~IR3_INSTR_S2EN;
659 instr->cat5.samp = samp->iim_val;
660 instr->cat5.tex = tex->iim_val;
663 instr->srcs_count--;
664 for (unsigned i = 0; i < instr->srcs_count; i++) {
665 instr->srcs[i] = instr->srcs[i + 1];
688 foreach_instr (instr, &block->instr_list) {
693 assert(instr->deps_count == 0);
695 foreach_ssa_src (src, instr) {