Lines Matching refs:store
119 * safely store NIR i1s in a 32-bit reg while always containing either a 1 or
1164 struct ir3_instruction *store, *offset;
1170 store = ir3_STLW(b, offset, 0,
1177 store->opc = OPC_STL;
1179 store->cat6.dst_offset = nir_intrinsic_base(intr);
1180 store->cat6.type = utype_src(intr->src[0]);
1181 store->barrier_class = IR3_BARRIER_SHARED_W;
1182 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
1184 array_insert(b, b->keeps, store);
1890 /* This is a bit of a hack until ir3_context is converted to store SSA values
2850 /* In the indirect case, we only use a1.x to store the sampler
3832 /* Generate the per-output store instructions: */
4742 * are "written" from the PoV of traditional store-