Lines Matching refs:intr
883 emit_intrinsic_load_ubo_ldc(struct ir3_context *ctx, nir_intrinsic_instr *intr,
891 assert(nir_intrinsic_base(intr) == 0);
893 unsigned ncomp = intr->num_components;
894 struct ir3_instruction *offset = ir3_get_src(ctx, &intr->src[1])[0];
895 struct ir3_instruction *idx = ir3_get_src(ctx, &intr->src[0])[0];
899 ldc->cat6.d = nir_intrinsic_component(intr);
902 ir3_handle_bindless_cat6(ldc, intr->src[0]);
905 ir3_handle_nonuniform(ldc, intr);
912 nir_intrinsic_instr *intr)
916 unsigned base = nir_intrinsic_base(intr);
917 unsigned size = nir_intrinsic_range(intr);
921 struct ir3_instruction *offset = ir3_get_src(ctx, &intr->src[1])[0];
922 struct ir3_instruction *idx = ir3_get_src(ctx, &intr->src[0])[0];
927 ir3_handle_bindless_cat6(ldc, intr->src[0]);
938 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
950 src0 = ir3_get_src(ctx, &intr->src[0])[0];
972 if (nir_src_is_const(intr->src[1])) {
973 off += nir_src_as_uint(intr->src[1]);
976 src1 = ir3_get_src(ctx, &intr->src[1])[0];
983 if ((off + (intr->num_components * 4)) > 1024) {
987 unsigned off2 = off + (intr->num_components * 4) - 1024;
1006 for (int i = 0; i < intr->num_components; i++) {
1018 nir_intrinsic_instr *intr,
1023 unsigned offset = nir_intrinsic_base(intr);
1026 struct ir3_instruction *src0 = ir3_get_src(ctx, &intr->src[0])[0];
1052 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1056 struct ir3_instruction *ibo = ir3_ssbo_to_ibo(ctx, intr->src[0]);
1064 ir3_handle_bindless_cat6(resinfo, intr->src[0]);
1065 ir3_handle_nonuniform(resinfo, intr);
1079 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1086 offset = ir3_get_src(ctx, &intr->src[0])[0];
1087 base = nir_intrinsic_base(intr);
1090 create_immed(b, intr->num_components), 0);
1092 ldl->cat6.type = utype_dst(intr->dest);
1093 ldl->dsts[0]->wrmask = MASK(intr->num_components);
1098 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
1103 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1110 value = ir3_get_src(ctx, &intr->src[0]);
1111 offset = ir3_get_src(ctx, &intr->src[1])[0];
1113 base = nir_intrinsic_base(intr);
1114 wrmask = nir_intrinsic_write_mask(intr);
1117 assert(wrmask == BITFIELD_MASK(intr->num_components));
1122 stl->cat6.type = utype_src(intr->src[0]);
1132 nir_intrinsic_instr *intr,
1139 offset = ir3_get_src(ctx, &intr->src[0])[0];
1140 base = nir_intrinsic_base(intr);
1143 create_immed(b, intr->num_components), 0);
1149 load->cat6.type = utype_dst(intr->dest);
1150 load->dsts[0]->wrmask = MASK(intr->num_components);
1155 ir3_split_dest(b, dst, load, 0, intr->num_components);
1161 nir_intrinsic_instr *intr)
1167 value = ir3_get_src(ctx, &intr->src[0]);
1168 offset = ir3_get_src(ctx, &intr->src[1])[0];
1171 ir3_create_collect(b, value, intr->num_components), 0,
1172 create_immed(b, intr->num_components), 0);
1179 store->cat6.dst_offset = nir_intrinsic_base(intr);
1180 store->cat6.type = utype_src(intr->src[0]);
1204 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1210 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
1211 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
1213 switch (intr->intrinsic) {
1245 src1 = ir3_collect(b, ir3_get_src(ctx, &intr->src[2])[0], src1);
1288 emit_intrinsic_load_scratch(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1295 stp_ldp_offset(ctx, &intr->src[0], &offset, &base);
1298 create_immed(b, intr->num_components), 0);
1300 ldp->cat6.type = utype_dst(intr->dest);
1301 ldp->dsts[0]->wrmask = MASK(intr->num_components);
1306 ir3_split_dest(b, dst, ldp, 0, intr->num_components);
1311 emit_intrinsic_store_scratch(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1319 value = ir3_get_src(ctx, &intr->src[0]);
1321 stp_ldp_offset(ctx, &intr->src[1], &offset, &base);
1323 wrmask = nir_intrinsic_write_mask(intr);
1326 assert(wrmask == BITFIELD_MASK(intr->num_components));
1331 stp->cat6.type = utype_src(intr->src[0]);
1431 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1437 if (!(nir_intrinsic_access(intr) & ACCESS_CAN_REORDER)) {
1438 ctx->funcs->emit_intrinsic_load_image(ctx, intr, dst);
1446 !ir3_bindless_resource(intr->src[0]) &&
1447 !nir_src_is_const(intr->src[0])) {
1448 ctx->funcs->emit_intrinsic_load_image(ctx, intr, dst);
1453 struct tex_src_info info = get_image_ssbo_samp_tex_src(ctx, &intr->src[0]);
1455 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &intr->src[1]);
1457 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1458 type_t type = ir3_get_type_for_image_intrinsic(intr);
1465 enum glsl_sampler_dim dim = nir_intrinsic_image_dim(intr);
1480 ir3_handle_nonuniform(sam, intr);
1491 nir_intrinsic_instr *intr,
1495 struct tex_src_info info = get_image_ssbo_samp_tex_src(ctx, &intr->src[0]);
1497 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1498 type_t dst_type = nir_dest_bit_size(intr->dest) == 16 ? TYPE_U16 : TYPE_U32;
1501 assert(nir_src_as_uint(intr->src[1]) == 0);
1534 nir_intrinsic_instr *intr,
1538 if (!(nir_intrinsic_access(intr) & ACCESS_CAN_REORDER) ||
1539 !ir3_bindless_resource(intr->src[0]) ||
1540 intr->dest.ssa.num_components > 1) {
1541 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1546 struct ir3_instruction *offset = ir3_get_src(ctx, &intr->src[2])[0];
1548 struct tex_src_info info = get_image_ssbo_samp_tex_src(ctx, &intr->src[0]);
1550 unsigned num_components = intr->dest.ssa.num_components;
1552 emit_sam(ctx, OPC_ISAM, info, utype_for_size(intr->dest.ssa.bit_size),
1555 ir3_handle_nonuniform(sam, intr);
1587 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1596 switch (intr->intrinsic) {
1601 nir_scope exec_scope = nir_intrinsic_execution_scope(intr);
1602 nir_variable_mode modes = nir_intrinsic_memory_modes(intr);
1607 nir_intrinsic_memory_semantics(intr) & (NIR_MEMORY_ACQUIRE |
1792 nir_intrinsic_barycentric_sysval(nir_intrinsic_instr *intr)
1794 enum glsl_interp_mode interp_mode = nir_intrinsic_interp_mode(intr);
1797 switch (intr->intrinsic) {
1824 emit_intrinsic_barycentric(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1827 gl_system_value sysval = nir_intrinsic_barycentric_sysval(intr);
1857 get_frag_coord(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1885 ctx->so->fragcoord_compmask |= nir_ssa_def_components_read(&intr->dest.ssa);
1971 emit_intrinsic_reduce(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1973 struct ir3_instruction *src = ir3_get_src(ctx, &intr->src[0])[0];
1974 nir_op nir_reduce_op = (nir_op) nir_intrinsic_reduction_op(intr);
1976 unsigned dst_size = nir_dest_bit_size(intr->dest);
2021 switch (intr->intrinsic) {
2032 static void setup_input(struct ir3_context *ctx, nir_intrinsic_instr *intr);
2033 static void setup_output(struct ir3_context *ctx, nir_intrinsic_instr *intr);
2036 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
2038 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
2042 unsigned dest_components = nir_intrinsic_dest_components(intr);
2046 dst = ir3_get_dst(ctx, &intr->dest, dest_components);
2055 switch (intr->intrinsic) {
2057 idx = nir_intrinsic_base(intr);
2058 if (nir_src_is_const(intr->src[0])) {
2059 idx += nir_src_as_uint(intr->src[0]);
2063 nir_dest_bit_size(intr->dest) == 16 ? TYPE_F16 : TYPE_F32);
2066 src = ir3_get_src(ctx, &intr->src[0]);
2070 nir_dest_bit_size(intr->dest) == 16 ? TYPE_F16 : TYPE_F32,
2107 idx = nir_intrinsic_driver_location(intr);
2151 ctx->funcs->emit_intrinsic_store_global_ir3(ctx, intr);
2154 ctx->funcs->emit_intrinsic_load_global_ir3(ctx, intr, dst);
2158 emit_intrinsic_load_ubo(ctx, intr, dst);
2161 emit_intrinsic_load_ubo_ldc(ctx, intr, dst);
2164 emit_intrinsic_copy_ubo_to_uniform(ctx, intr);
2167 ir3_split_dest(b, dst, get_frag_coord(ctx, intr), 0, 4);
2174 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
2192 emit_intrinsic_barycentric(ctx, intr, dst);
2196 setup_input(ctx, intr);
2199 emit_intrinsic_load_kernel_input(ctx, intr, dst);
2206 emit_intrinsic_load_ssbo(ctx, intr, dst);
2209 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
2212 emit_intrinsic_ssbo_size(ctx, intr, dst);
2224 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
2227 emit_intrinsic_load_shared(ctx, intr, dst);
2230 emit_intrinsic_store_shared(ctx, intr);
2242 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
2245 emit_intrinsic_load_scratch(ctx, intr, dst);
2248 emit_intrinsic_store_scratch(ctx, intr);
2252 emit_intrinsic_load_image(ctx, intr, dst);
2256 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
2260 ctx->funcs->emit_intrinsic_image_size(ctx, intr, dst);
2282 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
2292 emit_intrinsic_barrier(ctx, intr);
2297 setup_output(ctx, intr);
2328 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id)
2360 idx = nir_intrinsic_ucp_id(intr);
2446 if (intr->intrinsic == nir_intrinsic_discard_if ||
2447 intr->intrinsic == nir_intrinsic_demote_if ||
2448 intr->intrinsic == nir_intrinsic_terminate_if) {
2450 src = ir3_get_src(ctx, &intr->src[0]);
2467 if (intr->intrinsic == nir_intrinsic_demote ||
2468 intr->intrinsic == nir_intrinsic_demote_if) {
2493 src = ir3_get_src(ctx, &intr->src[0]);
2517 struct ir3_instruction *src = ir3_get_src(ctx, &intr->src[0])[0];
2519 if (intr->intrinsic == nir_intrinsic_vote_any)
2540 struct ir3_instruction *src = ir3_get_src(ctx, &intr->src[0])[0];
2541 struct ir3_instruction *cond = ir3_get_src(ctx, &intr->src[1])[0];
2552 struct ir3_instruction *src = ir3_get_src(ctx, &intr->src[0])[0];
2561 unsigned components = intr->dest.ssa.num_components;
2562 if (nir_src_is_const(intr->src[0]) && nir_src_as_bool(intr->src[0])) {
2566 struct ir3_instruction *src = ir3_get_src(ctx, &intr->src[0])[0];
2582 struct ir3_instruction *src = ir3_get_src(ctx, &intr->src[0])[0];
2583 struct ir3_instruction *idx = ir3_get_src(ctx, &intr->src[1])[0];
2585 type_t dst_type = type_uint_size(nir_dest_bit_size(intr->dest));
2596 struct ir3_instruction *src = ir3_get_src(ctx, &intr->src[0])[0];
2598 dst[0]->cat5.type = type_uint_size(nir_dest_bit_size(intr->dest));
2603 struct ir3_instruction *src = ir3_get_src(ctx, &intr->src[0])[0];
2605 dst[0]->cat5.type = type_uint_size(nir_dest_bit_size(intr->dest));
2610 struct ir3_instruction *src = ir3_get_src(ctx, &intr->src[0])[0];
2612 dst[0]->cat5.type = type_uint_size(nir_dest_bit_size(intr->dest));
2617 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
2620 emit_intrinsic_store_shared_ir3(ctx, intr);
2623 dst[0] = ir3_get_src(ctx, &intr->src[0])[0];
2635 dst[0] = ctx->funcs->emit_intrinsic_atomic_global(ctx, intr);
2642 dst[0] = emit_intrinsic_reduce(ctx, intr);
2652 unsigned components = nir_src_num_components(intr->src[0]);
2653 unsigned dst = nir_intrinsic_base(intr);
2658 ir3_create_collect(b, ir3_get_src(ctx, &intr->src[0]), components);
2682 nir_intrinsic_infos[intr->intrinsic].name);
2687 ir3_put_dst(ctx, &intr->dest);
3911 setup_input(struct ir3_context *ctx, nir_intrinsic_instr *intr)
3916 if (intr->intrinsic == nir_intrinsic_load_interpolated_input)
3917 coord = ir3_create_collect(ctx->block, ir3_get_src(ctx, &intr->src[0]), 2);
3919 compile_assert(ctx, nir_src_is_const(intr->src[coord ? 1 : 0]));
3921 unsigned frac = nir_intrinsic_component(intr);
3922 unsigned offset = nir_src_as_uint(intr->src[coord ? 1 : 0]);
3923 unsigned ncomp = nir_intrinsic_dest_components(intr);
3924 unsigned n = nir_intrinsic_base(intr) + offset;
3925 unsigned slot = nir_intrinsic_io_semantics(intr).location + offset;
4113 setup_output(struct ir3_context *ctx, nir_intrinsic_instr *intr)
4116 nir_io_semantics io = nir_intrinsic_io_semantics(intr);
4118 compile_assert(ctx, nir_src_is_const(intr->src[1]));
4120 unsigned offset = nir_src_as_uint(intr->src[1]);
4121 unsigned n = nir_intrinsic_base(intr) + offset;
4122 unsigned frac = nir_intrinsic_component(intr);
4123 unsigned ncomp = nir_intrinsic_src_components(intr, 0);
4226 struct ir3_instruction *const *src = ir3_get_src(ctx, &intr->src[0]);