ir3_compiler_nir.c - OpenGrok cross reference for /third_party/mesa3d/src/freedreno/ir3/ir3_compiler

Lines Matching refs:dsts
632       dst[0]->dsts[0]->flags |= IR3_REG_EI;
636       dst[0]->dsts[0]->flags |= IR3_REG_EI;
772       if (ctx->compiler->gen < 5 || (src[0]->dsts[0]->flags & IR3_REG_HALF)) {
791       hi->dsts[0]->flags |= IR3_REG_HALF;
792       lo->dsts[0]->flags |= IR3_REG_HALF;
795       dst[0]->dsts[0]->flags |= IR3_REG_HALF;
897    ldc->dsts[0]->wrmask = MASK(ncomp);
1063    resinfo->dsts[0]->wrmask = MASK(3);
1093    ldl->dsts[0]->wrmask = MASK(intr->num_components);
1150    load->dsts[0]->wrmask = MASK(intr->num_components);
1301    ldp->dsts[0]->wrmask = MASK(intr->num_components);
1986    identity->dsts[0]->flags |= IR3_REG_SHARED;
2175       offset->dsts[0]->wrmask = 0x3;
2348          ctx->samp_id->dsts[0]->flags |= IR3_REG_HALF;
2371          ctx->frag_face->dsts[0]->flags |= IR3_REG_HALF;
2393             ctx->work_group_id->dsts[0]->flags |= IR3_REG_SHARED;
2464       cond->dsts[0]->num = regid(REG_P0, 0);
2465       cond->dsts[0]->flags &= ~IR3_REG_SSA;
2503       cond->dsts[0]->num = regid(REG_P0, 0);
2544       dst[0]->dsts[0]->flags |= IR3_REG_SHARED;
2554       dst[0]->dsts[0]->flags |= IR3_REG_SHARED;
3261       sam->dsts[0]->wrmask = 0x7;
3412       __ssa_dst(continue_phi)->flags = phi->dsts[0]->flags;
3420             ir3_src_create(continue_phi, INVALID_REG, phi->dsts[0]->flags);
3460             ir3_src_create(phi, INVALID_REG, phi->dsts[0]->flags);
3799    cond->dsts[0]->num = regid(REG_P0, 0);
3800    cond->dsts[0]->flags &= ~IR3_REG_SSA;
3976          input->dsts[0]->wrmask |= compmask;
3985             ctx->inputs[idx]->srcs[0]->wrmask = input->dsts[0]->wrmask;
4575             fetch->wrmask = instr->dsts[0]->wrmask;
4576             fetch->dst = instr->dsts[0]->num;
4589             fetch->half_precision = !!(instr->dsts[0]->flags & IR3_REG_HALF);
4860          in->dsts[0]->num = so->nonbinning->inputs[inidx].regid;
4867       ctx->tcs_header->dsts[0]->num = regid(0, 0);
4868       ctx->rel_patch_id->dsts[0]->num = regid(0, 1);
4870          ctx->primitive_id->dsts[0]->num = regid(0, 2);
4877       ctx->gs_header->dsts[0]->num = regid(0, 0);
4879          ctx->primitive_id->dsts[0]->num = regid(0, 1);
4889          instr->dsts[0]->num = idx;
4940                ctx, in->dsts[0]->num == so->nonbinning->inputs[inidx].regid);
4941             compile_assert(ctx, !!(in->dsts[0]->flags & IR3_REG_HALF) ==
4947          so->inputs[inidx].regid = in->dsts[0]->num;
4948          so->inputs[inidx].half = !!(in->dsts[0]->flags & IR3_REG_HALF);